LTC1876 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC1876
Linear Technology
'LTC1876' PDF : 36 Pages View PDF
LTC1876
APPLICATIO S I FOR ATIO
signal ground pin and the ground return of CINTVCC must
return to the combined COUT (–) plates. Within the regula-
tor circuitry, are the signal and power grounds kept
separate? The regulator signal ground pin must return to
the CAUXIN (–) plates.
3. Does the path formed by the top N-Channel MOSFET
Schottky diode (D1, D2) and the CIN capacitor have short
leads and PC trace lengths? The output capacitor (–)
plates should be connected as close as possible to the
(–) plates of the input capacitor by placing the capacitors
next to each other and away from the Schottky loop
described above. Also, the path formed by the AUXSW
pins, Schottky diode (D3) and the COUT3 capacitor should
have short leads and PC trace lengths. The CAUXIN capaci-
tor (–) plates should be connected as close as possible to
the (–) plates of the COUT3 (–) plates by placing the
capacitors next to each other and away from the D3 loop
described above.
4. If the input supply to the boost regulator is obtain from
one of the other outputs, is this connection short (< 1cm)?
5. Do the LTC1876 VOSENSE and AUXVFB pins resistive
dividers connect to the (+) plates of its respective COUT?
The resistive divider must be connected between the (+)
plate of COUT and signal ground and a small VOSENSE
decoupling capacitor should be as close as possible to the
LTC1876 SGND pin. A feedforward capacitor across R8
can be connected to enhance the transient response of the
boost regulator. The R2, R4 and R8 connections should
not be along the high current input feeds from the input
capacitor(s).
SW1
L1
RSENSE1 VOUT1
+
D1
COUT1
RL1
VIN
RIN
+
CIN
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
SW2
D2
L2
RSENSE2 VOUT2
+
COUT2
Figure 16. Branch Current Waveforms
RL2
1876 F16
1876fa
31
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