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LTC1960CUHF-TRPBF View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
LTC1960CUHF-TRPBF
Linear
Linear Technology Linear
'LTC1960CUHF-TRPBF' PDF : 28 Pages View PDF
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LTC1960
APPLICATIONS INFORMATION
IDRIVE is the fixed drive current into the gate from the
LTC1960 and “t” is the time it takes to move that charge
to a new state and change the MOSFET conduction mode.
Hence, time is directly related to QGATE. Since QGATE
goes up with MOSFETs of lower RDS(ON), choosing such
MOSFETs has a counterproductive increase in gate charge
making the MOSFET slower. Please note that the LTC1960
recovery time specification only refers to the time it takes
for the voltage to recover to the level just prior to the
LOW_POWER event as opposed to full voltage.
The single pulse current rating of the MOSFET is important
when a short-circuit takes place. The MOSFET must survive
a 15ms overload. MOSFETs of lower RDS(ON) or MOSFETs
that use more powerful thermal packages will have a high
power surge rating. Using too small of a pulse rating will
allow the MOSFET to blow to the open-circuit condition
instantly like a fuse. Typically there is no outward sign of
failure because it happens so fast. Please measure the
surge current for all discharge power paths under worse
case conditions and consult the MOSFET data sheet for
the limitations. Voltage sources with the highest voltage
and the most bulk capacitance are often the biggest risk.
Specifically the MOSFETs in the wall adapter path with wall
adapters of high voltage, large bulk capacitance and low
resistance DC cables between the adapter and device are
the most common failures. Remember to only use the real
wall adapter with a production DC power cord when per-
forming the wall adapter path test. The use of a laboratory
power supply is unrealistic for this test and will force you
to over specify the MOSFET ratings. A battery pack usu-
ally has enough series resistance to limit the peak current
or are too low in voltage to create enough instantaneous
power to damage their respective PowerPath MOSFETs.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
time is kept as short as possible. To prevent magnetic
and electrical field radiation and high frequency resonant
problems, proper layout of the components connected to
the IC is essential.
1. Keep the highest frequency loop path as small and
tight as possible. This includes the bypass capacitors,
with the higher frequency capacitors being closer to
the noise source than the lower frequency capacitors.
24
The highest frequency switching loop has the highest
layout priority. For best results, avoid using vias in this
loop and keep the entire high frequency loop on a single
external PCB layer. If you must, use multiple vias to keep
the impedance down (see Figure 9).
SWITCH NODE
HIGH
VIN
CIN
FREQUENCY
CIRCULATING
PATH
L1
VBAT
D1
COUT
BAT
1960 F09
Figure 9. High Speed Switching Path
2. Run long power traces in parallel. Best results are
achieved if you run each trace on separate PCB layer one
on top of the other for maximum capacitance coupling
and common mode noise rejection.
3. If possible, use a ground plane under the switcher
circuitry to minimize capacitive interplane noise cou-
pling.
4. Keep signal or analog ground separate. Tie this analog
ground back to the power supply at the output ground
using a single point connection.
5. For best current programming accuracy provide a Kelvin
connection from RSENSE to CSP and CSN. See Figure  10
as an example.
DIRECTION OF CHARGING CURRENT
RSNS
1960 F10
CSP
CSN
Figure 10. Kelvin Sensing of Charging Current
1960fb
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