LTC2204 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2204' PDF : 36 Pages View PDF
LTC2205/LTC2204
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2205/LTC2204 are CMOS pipelined multistep
converters with a front-end PGA. As shown in Figure 1, the
converter has five pipelined ADC stages; a sampled analog
input will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2205/LTC2204 have two phases of operation,
determined by the state of the differential ENC+/ENC– input
pins. For brevity, the text will refer to ENC+ greater
than ENC– as ENC high and ENC+ less than ENC– as
ENC low.
Each pipelined stage shown in Figure 1 contains an
ADC, a reconstruction DAC and a residue amplifier. In
operation, the ADC quantizes the input to the stage, and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the voltage on the
sample capacitors is held. While ENC is high, the held
input voltage is buffered by the S/H amplifier which drives
the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fifth stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
LTC2005/LTC2004
VDD
RPARASITIC
3Ω
AIN+
VDD
RPARASITIC
3Ω
AIN–
VDD
CPARASITIC
1.8pF
CPARASITIC
1.8pF
RON
CSAMPLE
4.9pF
20Ω
CSAMPLE
RON 4.9pF
20Ω
20
ENC+
ENC–
1.6V
6k
6k
1.6V
Figure 2. Equivalent Input Circuit
22054 F02
22054fc
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