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LTC2239IUH View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
LTC2239IUH
Linear
Linear Technology Linear
'LTC2239IUH' PDF : 20 Pages View PDF
LTC2239
APPLICATIO S I FOR ATIO
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range) OF
D9 – D0
(Offset Binary)
>+1.000000V 1
+0.998047V 0
+0.996094V 0
11 1111 1111
11 1111 1111
11 1111 1110
+0.001953V 0
0.000000V 0
–0.001953V 0
–0.003906V 0
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
–0.998047V 0
–1.000000V 0
<–1.000000V 1
00 0000 0001
00 0000 0000
00 0000 0000
D9 – D0
(2’s Complement)
01 1111 1111
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
10 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50to external
circuitry and may eliminate the need for external damping
resistors.
LTC2239
VDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
OE
OVDD 0.5V
VDD
TO 3.6V
0.1µF
OVDD
43
TYPICAL
DATA
OUTPUT
OGND
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2239 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2239 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3VDD selects offset
binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format.
An external resistor divider can be used to set the 1/3VDD
or 2/3VDD logic values. Table 2 shows the logic states for
the MODE pin.
Table 2. MODE Pin Function
MODE Pin
0
1/3VDD
2/3VDD
VDD
Output Format
Offset Binary
Offset Binary
2’s Complement
2’s Complement
Clock Duty
Cycle Stablizer
Off
On
On
Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
2239 F12
Figure 14. Digital Output Buffer
2239fa
17
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