LTC2263-14 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2263-14' PDF : 32 Pages View PDF
LTC2265-14/
LTC2264-14/LTC2263-14
APPLICATIONS INFORMATION
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-14. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-14) or 25MHz (LTC2263-14).
SERIALIZATION MODE
2-Lane
16-Bit Serialization
2-Lane
14-Bit Serialization
2-Lane
12-Bit Serialization
1-Lane
16-Bit Serialization
1-Lane
14-Bit Serialization
1-Lane
12-Bit Serialization
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
65
65
65
62.5
65
65
DCO FREQUENCY
4 • fS
3.5 • fS
3 • fS
8 • fS
7 • fS
6 • fS
FR FREQUENCY
fS
0.5 • fS
fS
fS
fS
fS
SERIAL DATA RATE
8 • fS
7 • fS
6 • fS
16 • fS
14 • fS
12 • fS
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current can
be adjusted by control register A2 in serial programming
mode. Available current levels are 1.75mA, 2.1mA, 2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
D13-D0
(OFFSET BINARY)
>1.000000V
11 1111 1111 1111
+0.999878V
11 1111 1111 1111
+0.999756V
11 1111 1111 1110
+0.000122V
10 0000 0000 0001
+0.000000V
10 0000 0000 0000
–0.000122V
01 1111 1111 1111
–0.000244V
01 1111 1111 1110
–0.999878V
00 0000 0000 0001
–1.000000V
00 0000 0000 0000
≤–1.000000V
00 0000 0000 0000
D13-D0
(2’s COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
amplitude.
22654314f
23
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