LTC2264IUJ-12-TRPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2264IUJ-12-TRPBF' PDF : 32 Pages View PDF
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-12. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-12) or 25MHz (LTC2263-12).
SERIALIZATION MODE
2-Lane
16-Bit Serialization
2-Lane
14-Bit Serialization
2-Lane
12-Bit Serialization
1-Lane
16-Bit Serialization
1-Lane
14-Bit Serialization
1-Lane
12-Bit Serialization
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
65
65
65
62.5
65
65
DCO FREQUENCY
4 • fS
3.5 • fS
3 • fS
8 • fS
7 • fS
6 • fS
FR FREQUENCY
fS
0.5 • fS
fS
fS
fS
fS
SERIAL DATA RATE
8 • fS
7 • fS
6 • fS
16 • fS
14 • fS
12 • fS
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current can
be adjusted by control register A2 in serial programming
mode. Available current levels are 1.75mA, 2.1mA, 2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
In addition to the 12 data bits (D11 - D0), two additional
bits (DX and DY) are sent out in the 14-bit and 16-bit
serialization modes. These extra bits are to ensure com-
plete software compatibility with the 14-bit versions of
these A/Ds. During normal operation when the analog
inputs are not overranged, DX and DY are always logic 0.
When the analog inputs are overranged positive, DX and DY
become logic 1. When the analog inputs are overranged
negative, DX and DY become logic 0. DX and DY can also
be controlled by the digital output test pattern. See the
Timing Diagrams section for more information.
Table 2. Output Codes vs Input Voltage
AIN+ – AIN–
D11-D0
D11-D0
(2V RANGE) (OFFSET BINARY) (2’s COMPLEMENT)
>+1.000000V 1111 1111 1111 0111 1111 1111
+0.999512V 1111 1111 1111 0111 1111 1111
+0.999024V 1111 1111 1110 0111 1111 1110
+0.000488V 1000 0000 0001 0000 0000 0001
0.000000V 1000 0000 0000 0000 0000 0000
–0.000488V 0111 1111 1111 1111 1111 1111
–0.000976V 0111 1111 1110 1111 1111 1110
–0.999512V 0000 0000 0001 1000 0000 0001
–1.000000V 0000 0000 0000 1000 0000 0000
≤–1.000000V 0000 0000 0000 1000 0000 0000
DX, DY
11
00
00
00
00
00
00
00
00
00
22654312f
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