LTC2265IUJ-14 View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC2265IUJ-14

14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

Linear Technology 

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LTC2265-14/

LTC2264-14/LTC2263-14

PAR/SER (Pin 35): Programming Mode Selection Pin.

Connect to ground to enable the serial programming

mode. CS, SCK, SDI and SDO become a serial interface

that controls the A/D operating modes. Connect to VDD

to enable parallel programming mode where CS, SCK,

SDI and SDO become parallel logic inputs that control a

reduced set of the A/D operating modes. PAR/SER should

be connected directly to ground or the VDD of the part and

not be driven by a logic signal.

VREF (Pin 36): Reference Voltage Output. Bypass to ground

with a 1μF ceramic capacitor, nominally 1.25V.

SENSE (Pin 38): Reference Programming Pin. Connect-

ing SENSE to VDD selects the internal reference and a

±1V input range. Connecting SENSE to ground selects

the internal reference and a ±0.5V input range. An external

reference between 0.625V and 1.3V applied to SENSE

selects an input range of ±0.8 • VSENSE.

LVDS OUTPUTS

The following pins are differential LVDS outputs. The

output current level is programmable. There is an op-

tional internal 100Ω termination resistor between the

pins of each LVDS output pair.

OUT2B–/OUT2B+, OUT2A–,OUT2A+ (Pins 19/20, 21/22):

Serial Data Outputs for Channel 2. In 1-lane output mode,

only OUT2A–/OUT2A+ are used.

FR–/FR+ (Pin 23/Pin 24): Frame Start Output.

DCO–/DCO+ (Pin 27/Pin 28): Data Clock Output.

OUT1B–/OUT1B+, OUT1A–/OUT1A+ (Pins 29/30, 31/32):

Serial Data Outputs for Channel 1. In 1-lane output mode,

only OUT1A–/OUT1A+ are used.

22654314f

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