LTC2272 View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC2272

16-Bit, 80Msps/65Msps Serial Output ADC

Linear Technology 

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APPLICATIONS INFORMATION

LTC2273/LTC2272

AIN+

ANALOG

S/H

INPUT

AMP

AIN–

16-BIT

PIPELINED

ADC CORE

DIGITAL

SUMMATION

LTC2273/LTC2272

8b10b

ENCODER

SERIALIZER

CMLOUT+

CMLOUT–

CLOCK/DUTY

CYCLE

CONTROL

PRECISION

DAC

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

GENERATOR

ENC + ENC –

DITH

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit

22732 F11

SERIALIZED DATA FRAME

Prior to serialization, the ADC data is encoded into the

8B/10B format, which is DC balanced, and run-length

limited. The receiver is required to lock onto the data

and recover the clock with the use of a PLL. The 8B/10B

format requires that the ADC data be broken up into 8-bit

blocks (octets), which is encoded into 10-bit code groups

applying the 8B/10B rules (refer to IEEE Std 802.3-2002

Part 3, for a complete 8B/10B description).

Figure 12 illustrates the generation of one complete 8B/10B

frame. The 8 most significant bits of the ADC are assigned

to the first half of the frame, and the remaining 8 bits

to the second half of the frame. Next, the two resulting

octets are optionally scrambled and encoded into their

corresponding 8B/10B code. Finally, the two 10-bit code

groups are serialized and transmitted beginning with Bit

0 of code group 1.

MSB

ADC OUTPUT WORD

LSB

BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

H

G

F

E

D

C

B

A

BIT BIT BIT BIT BIT BIT BIT BIT

7

6

5

4

3

2

1

0

FIRST OCTET

H

G

F

E

D

C

B

A

BIT BIT BIT BIT BIT BIT BIT BIT

7

6

5

4

3

2

1

0

SECOND OCTET

H

G

F

E

D

C

B

A

BIT BIT BIT BIT BIT BIT BIT BIT

7

6

5

4

3

2

1

0

FIRST SCRAMBLED OCTET

H

G

F

E

D

C

B

A

BIT BIT BIT BIT BIT BIT BIT BIT

7

6

5

4

3

2

1

0

SECOND SCRAMBLED OCTET

a

b

c

d

e

i

f

g

h

j

BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT

0

1

2

3

4

5

6

7

8

9

8B/10B CODE GROUP 1

a

b

c

d

e

i

f

g

h

j

BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT

0

1

2

3

4

5

6

7

8

9

8B/10B CODE GROUP 2

BIT 0 OF CODE GROUP 1 IS TRANSMITTED FIRST

ONE FRAME

SERIAL OUT

22732 F12

Figure 12. Evolution of One Transmitted Frame (Compare to IEEE Std 802.3-2002 Part 3, Figure 36-3)

OCTET

ASSIGNMENT

OPTIONAL

SCRAMBLER

8B/10B

ENCODER

22732f

27

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