LTC2299 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2299' PDF : 24 Pages View PDF
LTC2299
APPLICATIO S I FOR ATIO
SINUSOIDAL
CLOCK
INPUT
4.7µF
0.1µF 1k
CLEAN
SUPPLY
FERRITE
BEAD
0.1µF
CLK LTC2299
50Ω 1k NC7SVU04
4.7µF
CLEAN
SUPPLY
FERRITE
BEAD
0.1µF
100Ω
CLK LTC2299
2299 F11
Figure 11. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2299 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
2299 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
DIFFERENTIAL
CLOCK
INPUT
ETC1-1T
CLK LTC2299
5pF-30pF
0.1µF FERRITE
BEAD
2299 F13
VCM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
2299fa
16
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