LTC2668 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC2668
Linear Technology
'LTC2668' PDF : 28 Pages View PDF
LTC2668
Operation
While the minimum input word is 24 bits, it may option-
ally be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits must be transferred to the device first,
followed by the 24-bit word, as just described. Figure 3b
shows the 32-bit sequence. The 32-bit word is required
for echo readback and daisy-chain operation, and is also
available to accommodate processors that have a minimum
word width of 16 or more bits.
Input and DAC Registers
The LTC2668 has five internal registers for each DAC, in
addition to the main shift register (see the Block Diagram).
Each DAC channel has two sets of double-buffered reg-
isters: one set for the code data, and one set for the span
(output range) of the DAC. Double buffering provides the
capability to simultaneously update the span and code,
which allows smooth voltage transitions when changing
output ranges. It also permits the simultaneous updating
of multiple DACs.
Each set of double-buffered registers comprises an input
register and a DAC register:
• Input Register: The write operation shifts data from the
SDI pin into a chosen input register. The input registers
are holding buffers; write operations do not affect the
DAC outputs.
In the code data path, there are two input registers, A
and B, for each DAC register. Register B is an alternate
input register used only in the toggle operation, while
register A is the default input register (see the Block
Diagram).
• DAC Register: The update operation copies the contents
of an input register to its associated DAC register. The
content of a DAC register directly controls the DAC
output voltage or range. The update operation also
powers up the selected DAC if it had been in power-
down mode. The data path and registers are shown in
the Block Diagram.
Note that updates always refresh both code and span
data, but the values held in the DAC registers remain
unchanged unless the associated input register values
have been changed via a write operation. For example, if
you write a new code and update the channel, the code
is updated, while the span is refreshed unchanged. A
channel update can come from a serial update com-
mand, an LDAC negative pulse, or a toggle operation.
Table 3. Write Span Code
OUTPUT RANGE
S2 S1 S0 INTERNAL REFERENCE EXTERNAL REFERENCE
0 00
0 01
0 10
0 11
1 00
0V TO 5V
0V to 10V
±5V
±10V
±2.5V
0V to 2VREF
0V to 4VREF
±2VREF
±4VREF
±VREF
Output Ranges
The LTC2668 is a 16-channel DAC with selectable output
ranges. Ranges can either be programmed in software or
hardwired through pin strapping.
SoftSpan Operation
SoftSpan operation (ranges controlled through the serial
interface) is invoked by tying all three MSPAN pins (MSP2,
MSP1 and MSP0) to AVP (see Table 4). In SoftSpan con-
figuration, all channels initialize to zero-scale in 0V to 5V
range at power-on. The range and code of each channel
are then fully programmable.
Each channel has a set of double-buffered registers for
range information (see the Block Diagram). Program the
span input register using the Write Span n or Write Span All
commands (0110b and 1110b, respectively). Figure 4 shows
the syntax, and Table 3 shows the span codes and ranges.
As with the double-buffered code registers, update opera-
tions copy the span input registers to the associated span
DAC registers.
WRITE SPAN COMMAND
ADDRESS
DON’T CARE
SPAN CODE
0 1 1 0 A3 A2 A1 A0 X X X X X X X X X X X X X S2 S1 S0
2668 F04
Figure 4. Write Span Syntax
2668fa
18
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