LTC2668CUJ-12PBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC2668CUJ-12PBF
Linear Technology
'LTC2668CUJ-12PBF' PDF : 28 Pages View PDF
Timing Diagram
t1
t2
t3
t4
SCK
1
2
3
23
SDI
t5
t7
CS/LD
Figure 1. Serial Interface Timing
LTC2668
t6
24
t10
2668 F01
Operation
The LTC2668 is a family of 16-channel, ±10V digital-to-
analog converters with selectable output ranges and an
integrated precision reference. The DACs operate on posi-
tive 5V and bipolar ±15V supplies. The bipolar supplies can
operate as low as ±4.5V, and need not be symmetrical. In
addition, the negative V– supply can be operated at ground,
making the parts compatible with single-supply systems.
The outputs are driven by the bipolar supply rails.
The output amplifiers offer true rail-to-rail operation. When
drawing a load current from the V+ or V– rail, the output
voltage headroom with respect to that rail is limited by
the 60Ω typical channel resistance of the output devices.
See the graph, Headroom at Rails vs Output Current, in
the Typical Performance Characteristics section.
The LTC2668 is controlled using a cascadable 3-wire SPI/
Microwire-compatible interface with echo readback.
Power-On Reset
The outputs reset when power is first applied, making
system initialization consistent and repeatable. By tying
the MSPAN pins (MSP2, MSP1, MSP0) to GND and/or
AVP, you can select the initial output range and reset
code (zero- or mid-scale), as well as selecting between a
manual (fixed) range and SoftSpan operation. See Table 4
for pin configurations and available options.
Power Supply Sequencing and Start-Up
The supplies (AVP, OVP, V+ and V–) may be powered up
in any convenient order.
If an external reference is used, the voltage at REF should
be kept within the range –0.3V ≤ VREF ≤ AVP + 0.3V (see
the Absolute Maximum Ratings section). Particular care
should be taken to observe these limits during power
supply turn-on and turn-off sequences when the voltage
at AVP is in transition.
Supply bypassing is critical to achieving the best possible
performance. We recommend at least 1μF to ground on
AVP, V+ and V– supplies, and at least 0.1μF of low ESR
capacitance for each supply, as close to the device as
possible. The larger capacitor may be omitted for OVP.
Hot-plugging or hard switching of supplies is not recom-
mended, as power supply cable or trace inductances
combined with bypass capacitances can cause supply
voltage transients beyond absolute maximum ratings,
even if the bench supply has been carefully current-/
voltage-limited. During start-up, limit the supply inrush
currents to no more than 5A and supply slew rates to no
more than 5V/µs. Internal protection circuitry can be dam-
aged and long-term reliability adversely affected if these
requirements are not met.
For more information www.linear.com/LTC2668
2668fa
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