LTC2668CUJ-16 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC2668CUJ-16
Linear Technology
'LTC2668CUJ-16' PDF : 28 Pages View PDF
LTC2668
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Digital input low and high voltages are 0V and OVP, respectively.
LTC2668-16/LTC2668-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
AVP = 4.5V to 5.5V, OVP = 1.71V to 2.7V
t1
SDI Valid to SCK Setup
l
7
ns
t2
SDI Valid to SCK Hold
l
7
ns
t3
SCK HIGH Time
l 30
ns
t4
SCK LOW Time
l 30
ns
t5
CS/LD Pulse Width
l 15
ns
t6
LSB SCK High to CS/LD High
l
7
ns
t7
CS/LD Low to SCK High
l
7
ns
t8
SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF
t9
CLR Pulse Width
l
l 30
60
ns
ns
t10
CS/LD High to SCK Positive Edge
l
7
ns
t12
LDAC Pulse Width
l 15
ns
t13
CS/LD High to LDAC High or Low Transition
l 15
ns
SCK Frequency
50% Duty Cycle
l
15
MHz
t14
TGP High Time (Note 9)
l
1
µs
t15
TGP Low Time (Note 9)
l
1
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND
Note 3: For V– = GND, linearity is defined from code kL to code 2N – 1,
where N is the resolution and kL is the lower end code for which no output
limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is
defined from code 128 to code 65,535. For VREF = 2.5V and N = 12, kL = 8
and linearity is defined from code 8 to code 4095.
Note 4: 4.5V ≤ V+ ≤ 16.5V; –16.5V ≤ V– ≤ –4.5V or
V– = GND. VOUT is at least 1.4V below V+ and 1.4V above V–.
Note 5: DC crosstalk is measured with AVP = 5V, using the internal
reference. The conditions of one DAC channel are changed as specified,
and the output of an adjacent channel (at mid-scale) is measured before
and after the change.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 7: Temperature coefficient is calculated by first computing the ratio
of the maximum change in output voltage to the nominal output voltage.
The ratio is then divided by the specified temperature range.
Note 8: Gain-error and bipolar zero error specifications may be degraded
for reference input voltages less than 1.25V. See the Gain Error vs
Reference Input and Bipolar Zero vs Reference Input curves in the Typical
Performance Characteristics section.
Note 9: Guaranteed by design and not production tested.
Note 10: Internal reference on.
Note 11: I(V+) measured in ±10V span; outputs unloaded; all channels at
full scale. I(V–) measured in ±10V span; outputs unloaded; all channels
at negative full scale. Each DAC amplifier is internally loaded by a 40kΩ
feedback network, so supply currents increase as output voltages diverge
from 0V.
Note 12: Digital inputs at 0V or OVP.
Note 13: Internal reference mode. Load is 2k in parallel with 100pF
to GND.
Note 14: AVP = 5V, 0V to 5V range, internal reference mode. DAC is
stepped ±1LSB between half-scale and half-scale – 1LSB. Load is 2k in
parallel with 200pF to GND.
Note 15: DAC-to-DAC crosstalk is the glitch that appears at the output of
one DAC due to full-scale change at the output of another DAC. 0V to 10V
range with internal reference. The measured DAC is at mid-scale.
For more information www.linear.com/LTC2668
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