LTC2919C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'LTC2919C' PDF : 20 Pages View PDF
LTC2919
APPLICATIONS INFORMATION
To minimize errors arising from ADJ input bias and to
minimize loading on REF choose resistor RP1 (for positive
supply monitoring) or RN1 (for negative supply monitor-
ing) in the range of 5k to 100k.
For a positive-monitoring application, RP2 is then chosen
by:
RP2 = RP1(2VTRIP – 1)
For a negative-monitoring application:
RN2 = RN1(1 – 2VTRIP)
Note that the value VTRIP should be negative for a nega-
tive application.
The LTC2919 can also be used to monitor a single sup-
ply for both UV and OV. This may be accomplished with
three resistors, instead of the four required for two inde-
pendent supplies. Configurations are shown in Figure 3 and
Figure 4. RP4 or RN4 may be chosen as is RP1 or RN1 above.
For a given RP4, monitoring a positive supply:
RP5
=
RP4
VOV – VUV
VUV
( ) RP6
= RP4
2VUV
–1
VOV
VUV
For monitoring a negative supply with a given RN4:
RN4
RN5
RN6
–VMON
REF
ADJ1
+
–
ADJ2
+
–
0.5V +–
LOGIC
& OUT1
OPEN
OV
DRAIN
MOSFET
LOGIC
& OUT2
OPEN
UV
DRAIN
MOSFET
2919 F04
Figure 4. Setting UV and OV Trip Point for a Negative Supply
For example, consider monitoring a –5V supply at ±10%.
For this supply application: VOV = –5.575V and VUV =
–4.425V. Suppose we wish to consume about 5μA in the
divider, so RN4 = 100k. We then find RN5 = 21.0k, RN6 =
1.18M (nearest 1% standard values have been chosen).
VCC Monitoring/UVLO
The LTC2919 contains an accurate third -10% undervolt-
age monitor on the VCC pin. This monitor is fixed at a
nominal 11.5% below the VCC specified in the part num-
ber. The standard part (LTC2919-2.5) is configured to
monitor a 2.5V supply (UVLO threshold of 2.213V), but
versions to monitor 3.3V and 5.0V (UVLO of 2.921V and
4.425V, respectively) are available.
R N5
=
R N4
VUV – VOV
1 – VUV
( ) RN6 = RN4
1 – 2VUV
1 – VOV
1 – VUV
For applications that do not need VCC monitoring, the 2.5V
version should be used, and the UVLO will simply guaran-
tee that the VCC is above the minimum required for proper
threshold and timer accuracy before the timeout begins.
Setting the Reset Timeout
VMON
RP6
RP5
RP4
ADJ1
+
–
ADJ2
+
–
0.5V +–
LOGIC
& OUT1
OPEN
UV
DRAIN
MOSFET
LOGIC
&
OUT2
OPEN
OV
DRAIN
MOSFET
2919 F03
Figure 3. Setting UV and OV Trip Point for a Positive Supply
RST goes high after a reset timeout period set by the TMR
pin when the VCC and ADJ inputs are valid. This reset
timeout may be configured in one of three ways: internal
200ms, programmed by external capacitor and no timeout
(comparator mode).
In externally-controlled mode, the TMR pin is connected
by a capacitor to ground. The value of that capacitor allows
for selection of a timeout ranging from about 400μs to 9
seconds. See the following section for details.
Rev. A
For more information www.analog.com
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