LTC2925C View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2925C' PDF : 24 Pages View PDF
LTC2925
APPLICATIONS INFORMATION
pin is pulled low, the supplies are latched off, and the
FAULT pin is held low until the fault is cleared by taking
the ON pin below 0.4V.
The PGI pin, which is normally connected to the RST pin of
an external supply monitor, is pulled up with 10μA through
a Schottky diode allowing it to be pulled safely above VCC.
Since, PGTMR pulls up with a 10μA current source, the
capacitor, CPGTMR, required to configure the power good
timeout duration, tPGTMR, is determined from:
CPGTMR
=
10μA • tPGTMR
1.23V
If the power good timeout circuit is unused, tie PGTMR
low and float PGI.
The Ramp Buffer
The RAMPBUF pin provides a buffered version of the
RAMP pin voltage that drives the resistive dividers on the
TRACKx pins. When there is no external FET, it provides
up to 3mA to drive the resistors even though the GATE
pin only supplies 10μA (Figure 8). The RAMPBUF pin
also proves useful in systems with an external FET. Since
the track cell drives 0.8V on the TRACKx pins, if RTBx is
connected directly to the FET’s source, the TRACKx pin
could potentially pull up the FET’s source towards 0.8V
when the FET is off. RAMPBUF blocks this path.
Shutdown Outputs
In some applications it might be necessary to control
the shutdown or RUN/SS pins of the slave supplies. The
LTC2925 may not be able to supply the rated 1mA of current
from the FB1, FB2, and FB3 pins when VCC is below 2.9V.
If the slave power supplies are capable of operating at low
input voltages, use the open-drain SDx outputs to drive
the SHDN or RUN/SS pins of the slave supplies (Figures 7
VIN
0.1μF
CGATE
RONB
RONA
VIN
VIN
RTB1
RTA1
RTB2
RTA2 RTB3
RTA3
VCC SENSEP SENSEN GATE
ON
REMOTE
RAMP
PGI
SD1
FB1
SUPPLY
MONITOR
RST
VIN
RUN/SS IN
DC/DC
FB
OUT
STATUS
FAULT
RAMPBUF
TRACK1
TRACK2
TRACK3
GND SCTMR
LTC2925
SD2
FB2
SD3
FB3
SDTMR PGTMR
CSDTMR
CPGTMR
RFA1
RFB1
VIN
RUN/SS IN
DC/DC
FB
OUT
RFA2
RFB2
VIN
RUN/SS IN
DC/DC
FB
OUT
RFB3
RFA3
2925 F08
SLAVE1
SLAVE2
SLAVE3
Figure 8. Typical Application Without External FET
and 8). The SDx pins are released when the ON pin rises
above 1.23V, VCC is above the 2.6V undervoltage lockout
condition, and there are no faults latched. The shutdown
timer begins at the same time, and the supplies begin to
ramp up after the shutdown timer cycle completes. The
duration of the timer cycle is configured by a capacitor
tied between SDTMR and GND. The capacitor voltage is
ramped up by a 10μA current source and the SDTMR
cycle completes when its voltage reaches 1.23V. Thus, the
capacitor, CSDTMR, required for a given shutdown timer
cycle, tSDTMR, is determined from:
CSDTMR
=
10μA • tSDTMR
1.23V
The SDx pins pull low again when the ON pin is pulled
below 1.23V and the RAMP pin is below about 100mV.
2925fc
11
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