LTC2925I View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2925I' PDF : 26 Pages View PDF
LTC2925
APPLICATIONS INFORMATION
Optional External FET
Figure 7 illustrates how an optional external N-channel
FET can ramp up a single supply that becomes the mas-
ter signal. When used, the FET’s gate is tied to the GATE
pin and its source is tied to the RAMP pin. Under normal
operation, the GATE pin sources or sinks 10μA to ramp
the FET’s gate up or down at a rate set by the external
capacitor connected to the GATE pin.
The series FET easily controls any supply with an output
voltage between 0V and VCC. See the Typical Applications
section for examples.
RSENSE
Q1
VIN
0.1μF
10Ω
CGATE
RONB
RONA
VIN
VCC SENSEP SENSEN GATE
ON
REMOTE
RAMP
PGI
SD1
FB1
MASTER
SUPPLY
MONITOR
RST
3.3V
RUN/SS IN
DC/DC
FB = 1.235V OUT
10k
VIN
10k
RTB1
RTA1
RTB2
RTA2 RTB3
RTA3
STATUS
LTC2925
SD2
FAULT
FB2
RAMPBUF
TRACK1
TRACK2
SD3
FB3
TRACK3
GND SCTMR SDTMR PGTMR
CSCTMR
CSDTMR
CPGTMR
RFA1
RFB1
3.3V
RUN/SS IN
DC/DC
FB = 0.8V OUT
RFA2
RFB2
3.3V
RUN/SS IN
DC/DC
FB = 0.8V OUT
RFB3
RFA3
2925 F07
Figure 7. Typical Application with External FET
1.8V
SLAVE1
2.5V
SLAVE2
1.5V
SLAVE3
Electronic Circuit Breaker
The LTC2925 features an electronic circuit breaker function
that protects the optional series FET against short circuits.
An external sense resistor is used to measure the current
flowing in the FET. If the voltage across the sense resistor
exceeds 50mV for more than a short-circuit timer cycle, the
gate of the FET is pulled low with 20mA, turning it off.
The short-circuit timer duration is configured by a capaci-
tor tied between SCTMR and GND. SCTMR will pull up
with 50μA when SENSEP – SENSEN > 50mV. Otherwise, it
pulls down with 2μA. When the voltage at SCTMR exceeds
1.23V, the GATE will be pulled to ground with 20mA and the
FAULT pin will be pulled low. Thus, the capacitor, CSCTMR,
required to configure the short-circuit timer duration,
tSCTMR is determined from:
CSCTMR
=
50μA • tSCTMR
1.23V
Because the slave supplies track the RAMP pin which is
driven by the external FET, they are pulled low by the track-
ing circuit when a short-circuit fault occurs. Following a
short-circuit fault, the FET is latched off and FAULT is pulled
low until the fault is cleared by pulling the ON pin below
0.4V. Note that the supplies will not be allowed to ramp up
again until SCTMR has been pulled below about 100mV by
the 2μA pull-down current source. The electronic circuit
breaker supports any supply voltage between 0V and VCC.
Although it is normally used to monitor current through
the optional series FET, it is capable of monitoring other
currents, including the current from a slave supply. The
Typical Applications section shows one such example.
If the electronic circuit breaker is not used, tie SENSEP
and SENSEN to VCC and SCTMR to GND.
Power Good Timeout
The power good timeout circuit turns off the supplies if an
external supply monitor, connected to the PGI pin, fails to
indicate that all supplies have entered regulation in time
after power up begins. After power up is complete, it turns
off the supplies if any supply exits regulation.
The power good timer duration is configured by a capaci-
tor tied between PGTMR and GND. PGTMR will pull up
the CPGTMR capacitor with 10μA starting when the ON
pin is driven above 1.23V. Once the voltage at the PGTMR
exceeds 1.23V, a fault will trip if the PGI pin is low. When
the power good timeout circuit detects a fault, the GATE
2925fc
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