LTC2926CGN View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2926CGN' PDF : 28 Pages View PDF
LTC2926
APPLICATIO S I FOR ATIO
SUPPLY
MODULE
OUT
SENSE
RX
ISW
+ VDS –
Q0
MGATE Q3
MASTER
SUPPLY
LOAD
RSGATE
(a)
VOUT
VSENSE
RX
ISW
+ VDS –
RDS
RSW
(b)
VSUPPLY
IL
2926 F11
Figure 11. Supply and Sense Path Detail, (a) Functional Diagram
and (b) Equivalent Circuit When Remote Sense Switch Is Closed
Considerations when Using Remote Sense Switches
Consider the supply and sense path detail functional
diagram and equivalent circuit in Figure 11. For proper
compensation of the I • R drop across the external control
MOSFET Q0 by the supply module, the voltage at its sense
pin input must be equal to the supply voltage at the load.
Solving for VSENSE in the equivalent circuit yields:
VSENSE
=
⎛
⎝⎜
RX
RX
+ RSW
⎞
⎠⎟
•
VSUPPLY
+
⎛
⎝⎜
RSW
RX + RSW
⎞
⎠⎟
•
VOUT
For the best compensation, i.e., VSENSE ≈ VSUPPLY, choose
RX >> RSW.
The remote sense switch is intended to be a low-current
voltage feedback path. The control MOSFET (Q0 in Figure
11a) should carry all but a tiny fraction of the entire load
current. The remote sense switch current is:
ISW
⎛
= ILOAD•⎝⎜
RX
+
RDS
RSW
+
RDS
⎞
⎠⎟
To minimize switch current, choose RX >> RDS. In appli-
cations that use the LTC2926’s integrated remote sense
switches, ISW must not exceed the Absolute Maximum
Ratings for switch pin currents.
It is recommended design practice to satisfy both
resistance value conditions.
SGATE Voltage at Ramp Start/End
When the master ramp is 0V (before ramp up or after
ramp down), the control MOSFET ideally conducts no
current. If the tracking profile has no delay or offset, the
gate control loops may force the SGATE pins either to
ground or to just below the MOSFET threshold voltage,
depending on reference offsets, resistor mismatches and
the load resistance. In both cases the slave load will be at
about 0V, but if a known state of SGATE is desired, include
an offset in the tracking profile.
To guarantee grounding of the SGATE pins at RAMP = 0V,
include a positive offset, VOS, based on the maximum slave
supply voltage, VSLAVE(max), and the tracking/feedback
resistor tolerance. Note that at the start of ramp up, the
gate capacitance of the MOSFET must be charged to the
threshold voltage before the source begins ramping. The
SGATE pins do provide extra current to speed the initial
charging.
Calculate the required VOS from:
VOS ≥ k • VSLAVE(max)
For 1% resistors k = 1/8, for 5% resistors k = 1/4, for
10% resistors k = 2/5.
To guarantee the SGATE pins sit at the MOSFET threshold
voltages at RAMP = 0V, include a negative offset. Note that
when the master ramp goes to 0V, the slave supplies will
remain above ground by the magnitude of the offset.
Calculate the required VOS from:
VOS ≤ –k • VSLAVE(max)
2926fa
16
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