LTC2942-1C View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC2942-1C
Linear Technology
'LTC2942-1C' PDF : 16 Pages View PDF
LTC2942-1
Applications Information
1000h at 1A current and 85°C ambient temperature; this
outperforms most types of discrete sense resistors except
those of the very high and ultrahigh stability variety. See
the Typical Performance Characteristics for expected
resistor drift performance under worst-case conditions.
Drift will be much slower at lower temperatures. Contact
LTC applications for more information.
For most coulomb counter applications this aging behavior
of the integrated sense resistor is insignificant compared
to the change of battery capacity due to battery aging.
The LTC2942-1 is factory trimmed to optimum accuracy
when new; for applications which require the best possible
coulomb count accuracy over the full product lifetime, the
coulomb counter gain can be adjusted in software. For
instance, if the error contribution of sense resistor drift
must be limited to ±1%, coulomb counts may be biased
high by 1% (use factor 1.01), and maximum operational
temperature and current then must be derated such that
sense resistor drift over product lifetime or calibration
intervals is less than –2%.
Applications employing the standard external resistor
LTC2942 with an external 50mΩ sense resistor may be
upgraded to the pin-compatible LTC2942-1 by removing
the external sense resistor.
Voltage Drop Between SENSE+ and SENSE–
The LTC2942-1 is trimmed for an effective internal resis-
tance of 50mΩ , but the total pin-to-pin resistance (RPP),
consisting of the sense resistor in series with pin and bond
wire resistances, is somewhat higher. Assuming a sense
resistor temperature coefficient of about 3900ppm/K,
the total resistance between SENSE+ and SENSE– at a
temperature T is typically:
RPP(T) = RPP(TNOM) [1 + 0.0039(T – TNOM)]
SDA
a6 - a0
b7 - b0
b7 - b0
SCL
S
START
CONDITION
1-7
ADDRESS
8
9
1-7
8
9
1-7
8
R/W
ACK
DATA
ACK
DATA
Figure 3. Data Transfer Over I2C or SMBus
9
P
ACK
STOP
CONDITION
29421 F03
S ADDRESS W A REGISTER A DATA A P
1100100 0 0
01h
0 FCh 0
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
29421 F04
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
Figure 4. Writing FCh to the LTC2942-1 Control Register (B)
S ADDRESS W A REGISTER A DATA A DATA A P
1100100 0 0
02h
0 F0h 0 01h 0
29421 F05
Figure 5. Writing F001h to the LTC2942-1
Accumulated Charge Register (C, D)
S ADDRESS W A REGISTER A S ADDRESS R A DATA A P
1100100 0 0
00h
0
1100100 1 0 01h 1
29421 F06
Figure 6. Reading the LTC2942-1 Status Register (A)
S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P
1100100 0 0
08h
0
1100100 1 0 F1h 0 24h 1
29421 F07
Figure 7. Reading the LTC2942-1 Voltage Register (I, J)
29421f
13
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