LTC3701 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC3701' PDF : 20 Pages View PDF
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OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3701 uses a constant frequency, current mode
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (ICMP) resets the latch. The
peak inductor current at which ICMP resets the RS latch is
controlled by the voltage on the ITH/RUN pin, which is the
output of each error amplifier, EAMP. The VFB pin receives
the voltage feedback signal, which is compared to the
internal reference voltage by the EAMP. When the load
current increases, it causes a slight decrease in VFB
relative to the 0.8V reference, which in turn, causes the ITH/
RUN voltage to increase until the average inductor current
matches the new load current.
Each main control loop is shut down by pulling the
respective ITH/RUN pin low. When both ITH/RUN1 and ITH/
RUN2 are low, all LTC3701 controller functions are shut
down. Releasing ITH/RUN allows an internal 0.5µA current
source to charge up the external compensation network.
When the ITH/RUN pin reaches 0.35V, the main control
loop is enabled with the ITH/RUN voltage then pulled up to
its zero current level of approximately 0.7V. After the loop
is enabled, an internal soft-start begins. During this soft-
start time of 2048 clock cycles, the ITH/RUN voltage is
clamped such that the maximum peak current sense
voltage (VSENSE + – VSENSE –) is held to approximately 0%,
25%, 50% and 75%, respectively, of its maximum value of
120mV for four equally timed intervals. After soft-start is
completed, full current operation is allowed. As the exter-
nal compensation network continues to charge, the corre-
sponding output current trip level follows, allowing normal
operation.
Comparator OVP guards against transient output voltage
overshoots greater than 10% by turning off the external
P-channel power MOSFET and keeping it off until the fault
is removed.
Burst Mode Operation
The LTC3701 can be enabled to enter Burst Mode opera-
tion at low load currents by tying the EXTCLK/MODE pin to
LTC3701
VIN or to a voltage of at least 2V. To disable Burst Mode
operation and enable PWM pulse skipping mode, connect
the EXTCLK/MODE pin to ground. In this mode, the
efficiency is lower at light loads. However, pulse skipping
mode has the advantages of lower output ripple and less
interference to audio circuitry.
When a controller is in Burst Mode operation, the peak
current of the inductor is set as if VITH/RUN = 1V, even
though the voltage at the ITH/RUN pin is at a lower value.
If the inductor’s average current is greater than the load
requirement, the voltage at the ITH/RUN pin will drop.
When the ITH/RUN voltage goes below 0.85V, the sleep
signal goes high, turning off the external MOSFET. The
sleep signal goes low when the ITH/RUN voltage goes
above 0.925V and that controller channel resumes normal
operation. The next oscillator cycle will turn the external
MOSFET on and the switching cycle repeats.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC3701 to
allow the internal oscillator to be synchronized to an
external clock source connected to the EXTCLK/MODE
pin. The output of the phase detector at the PLLLPF pin
operates over a 0V to 2.4V range corresponding to ap-
proximately 300kHz to 750kHz. When locked, the PLL
aligns the turn-on of the external MOSFET of controller
channel 1 to the rising edge of the synchronizing signal.
The turn-on of the external MOSFET of controller channel
2 is 180 degrees out of phase with the rising edge of the
external clock source.
When the LTC3701 is clocked by an external source, Burst
Mode operation is disabled and the LTC3701 operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, the current comparator ICMP may remain
tripped for several cycles and force the external MOSFET
to stay off for the same number of cycles. Increasing the
output load slightly allows constant frequency PWM op-
eration to resume. This mode exhibits low output ripple as
well as low audio noise and reduced RF interference while
providing reasonable low current efficiency.
3701fa
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