LTC3727EG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC3727EG' PDF : 32 Pages View PDF
LTC3727/LTC3727-1
APPLICATIO S I FOR ATIO
Design Example
As a design example for one channel, assume VIN =
24V(nominal), VIN = 30V(max), VOUT = 12V, IMAX = 5A and
f = 250kHz.
The inductance value is chosen first based on a 40% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR pin
to the SGND pin for 250kHz operation. The minimum
inductance for 40% ripple current is:
∆IL
=
VOUT
(f)(L)
1–
VOUT
VIN
A 14µH inductor will result in 40% ripple current. The peak
inductor current will be the maximum DC value plus one
half the ripple current, or 6A, for the 14µH value.
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE
≤
90mV
6A
≈
0.015Ω
Choosing 1% resistors; R1 = 20k and R2 = 280k yields an
output voltage of 12V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in; RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input
voltage with T(estimated) = 50°C:
PMAIN
=
12V
30V
(5)2[1+
(0.005)(50°C
–
25°C)]
(0.042Ω) + 1.7(30V)2(5A)(100pF)(250kHz)
= 664mW
A short-circuit to ground will result in a folded back current
of:
ISC
=
45mV
0.015Ω
+
1
2
200ns(30V)
14µH
=
3.2A
with a typical value of RDS(ON) and δ = (0.005/°C)(20) =
0.1. The resulting power dissipated in the bottom MOSFET
is:
PSYNC
=
30V – 12V
30V
(3.2A)2(1.1)(0.042Ω)
= 126mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω(2A) = 40mVP–P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3727. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
3727f
25
Share Link: 
