LTC3770EG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3770EG
Linear Technology
'LTC3770EG' PDF : 24 Pages View PDF
LTC3770
APPLICATIONS INFORMATION
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
The ITH pin external components shown in Figure 12 will
provide adequate compensation for most applications. For
a detailed explanation of switching control loop theory see
Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 5V to 28V (15V nominal), VOUT =
2.5V ±5%, IOUT(MAX) = 10A, f = 450kHz. First, calculate
the timing resistor with VON = VOUT:
RON
=
2.5V
3(2.5V)(450kHz)(10pF)
=
74kΩ
and choose the inductor for about 40% ripple current at
the maximum VIN :
L
=
2.5V
(450kHz ) (0.4)
(10A)
⎛
⎝⎜1−
2.5V
28V
⎞
⎠⎟
=
1.3μH
Selecting a standard value of 1.8μH results in a maximum
ripple current of:
ΔIL
=
2.5V
(450kHz ) (1.8μH)
⎛
⎝⎜1–
2.5V
28V
⎞
⎠⎟
=
2.8A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
20
Tying VRNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ150°C = 1.5:
ILIMIT
≥
146mV
(1.5)(0.010Ω)
+
1
2
(2.8A)
=
11A
and double check the assumed TJ in the MOSFET:
PBOT
=
28V – 2.5V
28 V
(11A
)2(1.5)(0.010Ω)
=
1.65W
TJ = 70°C + (1.65W)(40°C/W) = 136°C
Because the top MOSFET is on for such a short time, an
Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF, θJA =
40°C/W will be sufficient. Checking its power dissipation
at current limit with ρ100°C = 1.4:
PTOP
=
2.5V
28V
(11A
)2
(1.4)
(0.0165Ω)
+
(1.7)(28V)2 (11A)(100pF)(250kHz)
= 0.25W + 0.37W = 0.62W
TJ = 70°C + (0.62W)(40°C/W) = 95°C
The junction temperature will be significantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
CIN is chosen for an RMS current rating of about 3A at 85°C.
The output capacitors are chosen for a low ESR of 0.013Ω
to minimize output voltage changes due to inductor ripple
current and load steps. The ripple voltage will be only:
ΔVOUT(RIPPLE) =ΔIL(MAX) (ESR)
= (2.8A) (0.013Ω) = 36mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 12.
3770fc
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