LTC3776 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3776
Linear Technology
'LTC3776' PDF : 28 Pages View PDF
LTC3776
APPLICATIO S I FOR ATIO
Channel 2’s output voltage is set to 1/2 VREF by connecting
the VFB2 pin to VOUT2. To improve the frequency response,
a feed-forward capacitor, CFF, may be used. Great care
should be taken to route the VFB line away from noise
sources, such as the inductor or the SW line.
VOUT1
VOUT2
CFF RB
LTC3776
VFB1 VFB2
RA
3776 F06
Figure 6. Setting Output Voltage
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3776.
Pulling the RUN/SS pin below 0.65V puts the LTC3776 into
a low quiescent current shutdown mode (IQ = 9µA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3776 comes out of shutdown and
is given by:
tDELAY
=
0.65V
•
C SS
0.7µA
=
0.93s/µF
• CSS
This pin can be driven directly from logic as shown in
Figure 7. Diode D1 in Figure 7 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
3.3V OR 5V
RUN/SS
D1
RUN/SS
CSS
CSS
3776 F07
Figure 7. RUN/SS Pin Interfacing
18
During soft-start, the start-up of VOUT1 is controlled by
slowly ramping the positive reference to the error amplifier
from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V
to its final value. The default internal soft-start time is 1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time will
be approximately:
tSS1
=
CSS
•
600mV
0.7µA
VREF Pin
The regulation of VOUT2 is controlled by the voltage on the
VREF pin. Normally this pin is used in DDR memory
termination applications so that VOUT2 tracks 1/2 VOUT1 as
shown in Figure 8.
VOUT1
VOUT2
R1B LTC3776
VFB1
R1A
VFB2
VREF
3776 F08
Figure 8. Using the VREF Pin (VOUT2
is Regulated to 1/2 VREF = 1/2VOUT1)
Phase-Locked Loop and Frequency Synchronization
The LTC3776 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external
P-channel MOSFET of controller 1 to be locked to the
rising edge of an external clock signal applied to the
SYNC/SSEN pin. The turn-on of controller 2’s external
P-channel MOSFET is thus 180 degrees out of phase with
the external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
3776f
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