LTC3776 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3776
Linear Technology
'LTC3776' PDF : 28 Pages View PDF
LTC3776
APPLICATIO S I FOR ATIO
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3776. These items are illustrated in the layout diagram
of Figure 12. Figure 13 depicts the current waveforms
present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
at the FETs. It is better to have two separate, smaller valued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor
dividers, ITH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Each channel should have its own power ground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
The PGND pins on the LTC3776 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
output capacitor should be a Kelvin trace. The ITH compen-
sation components should also be very close to the
LTC3776.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, ITH compensation components and the current
sense pins (SENSE+ and SW).
LTC3776EGN
1
SW1
SENSE1+ 24
2
IPRG1
23
PGND
3
22
VFB1
BG1
4
21
ITH1 SYNC/SSEN
5
20
IPRG2
TG1
6
19
PLLLPF PGND
7
SGND
18
TG2
8
VIN
9
VREF
10
VFB2
11
ITH2
12
PGOOD
17
RUN/SS
16
BG2
15
PGND
SENSE2+ 14
13
SW2
COUT1
VOUT1
L1
MN1 MP1
CVIN1
CVIN
CVIN2
MN2
VIN
MP2
L2
COUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
VOUT2
3776 F12
Figure 12. LTC3776 Layout Diagram
3776f
21
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