LTC3776EUF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3776EUF
Linear Technology
'LTC3776EUF' PDF : 28 Pages View PDF
LTC3776
APPLICATIO S I FOR ATIO
frequency, when there is a clock signal applied to SYNC/
SSEN, is shown in Figure 9 and specified in the Electrical
Characteristics table. Note that the LTC3776 can only be
synchronized to an external clock whose frequency is
within range of the LTC3776’s internal VCO, which is
nominally 200kHz to 1MHz. This is guaranteed, over
temperature and process variations, to be between 250kHz
and 850kHz. A simplified block diagram is shown in
Figure 10.
1400
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2 2.4
PLLLPF PIN VOLTAGE (V)
3776 F09
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
EXTERNAL
OSCILLATOR
SYNC/
SSEN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
RLP
CLP
PLLLPF
OSCILLATOR
3776 F10
Figure 10. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor CLP holds the voltage.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
Typically, the external clock (on SYNC/SSEN pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
Floating
VIN
RC Loop Filter
Capacitor to
GND
SYNC/SSEN PIN
GND
GND
GND
Clock Signal
VIN
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked to External Clock
Spread Spectrum Operation
450kHz to 550kHz
Low Supply Operation
Although the LTC3776 can function down to below 2.4V,
the maximum allowable output current is reduced as VIN
decreases below 3V. Figure 11 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on VREF.
105
VREF
100
95
MAXIMUM
SENSE VOLTAGE
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3776 F11
Figure 11. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
3776f
19
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