LTC4088 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4088' PDF : 24 Pages View PDF
LTC4088
Applications Information
Voltage overshoot on VBUS may sometimes be observed
when connecting the LTC4088 to a lab power supply. This
overshoot is caused by long leads from the power supply
to VBUS. Twisting the wires together from the supply to
VBUS can greatly reduce the parasitic inductance of these
long leads, and keep the voltage at VBUS to safe levels. USB
cables are generally manufactured with the power leads in
close proximity, and thus fairly low parasitic inductance.
4088 F06
Board Layout Considerations
The Exposed Pad on the backside of the LTC4088 pack-
age must be securely soldered to the PC board ground.
This is the only ground pin in the package, and it serves
as the return path for both the control circuitry and the
synchronous rectifier.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitor, inductor, and
output capacitor be as close to the LTC4088 as possible
and that there be an unbroken ground plane under the
LTC4088 and all of its external high frequency components.
High frequency currents, such as the input current on the
LTC4088, tend to find their way on the ground plane along
a mirror path directly beneath the incident path on the top
of the board. If there are slits or cuts in the ground plane
due to other traces on that layer, the current will be forced
to go around the slits. If high frequency currents are not
allowed to flow back through their natural least-area path,
excessive voltage will build up and radiated emissions will
occur (see Figure 6). There should be a group of vias directly
under the grounded backside leading directly down to an
internal ground plane. To minimize parasitic inductance,
the ground plane should be as close as possible to the
top plane of the PC board (layer 2).
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an additional offset
to the ideal diode of approximately 10mV. To minimize
leakage, the trace can be guarded on the PC board by
surrounding it with VOUT connected metal, which should
generally be less than one volt higher than GATE.
20
Figure 6. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions
Battery Charger Stability Considerations
The LTC4088’s battery charger contains both a constant-
voltage and a constant-current control loop. The constant-
voltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance to
require a bypass capacitor of at least 1µF from BAT to GND.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22µF
may be used in parallel with a battery, but larger ceramics
should be decoupled with 0.2Ω to 1Ω of series resistance.
Furthermore, a 4.7µF capacitor in series with a 0.2Ω to 1Ω
resistor from BAT to GND is required to prevent oscillation
when the battery is disconnected.
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the charger
is stable with program resistor values as high as 25k.
However, additional capacitance on this node reduces the
maximum allowed program resistor. The pole frequency at
the PROG pin should be kept above 100kHz. Therefore, if
the PROG pin has a parasitic capacitance, CPROG, the fol-
lowing equation should be used to calculate the maximum
resistance value for RP ROG :
RPROG
≤
2π
1
• 100kHz
•
CPROG
4088fb
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