LTC4156IUFD View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC4156IUFD
Linear Technology
'LTC4156IUFD' PDF : 52 Pages View PDF
LTC4156
OPERATION
Low Power Ship-and-Store Mode
The LTC4156 can reduce its already low standby current
to approximately 1µA in a special mode designed for
shipment and storage. Unlike normal standby mode, in
this mode the external PMOS gate is driven to the battery
voltage to disable FET conduction through the external
PMOS. This mode may be used to cut off all power to
any downstream load on VOUT to maximize battery life
between product manufacture and sale. Note that the bulk
connection inside the external PMOS will provide a con-
ductive path from the battery to VOUT, independent of the
voltage on its gate. To block conduction to VOUT, typically
two PMOS transistors must be connected in series with
either the sources or drains of each device connected in
the center, as shown in Figure 4. If the application does
not require the battery to be isolated from downstream
devices, significant power savings in the LTC4156 may
still be realized by activating this mode.
Ship-and-store mode is armed following the acknowledge
of any data byte written to sub address 0x07 by the I2C
bus master. The contents of the data byte are ignored, but
the full byte and acknowledge clock cycle must be sent.
Ship-and-store mode is activated as VBUS falls below ap-
proximately 1V, or immediately if no input power is present
when the I2C command is issued. VBUS quiescent current
falls to nearly zero when power is removed from the USB
and WALL inputs, resulting in a delay of up to several hours
for VBUS to self-discharge to the 1V activation threshold.
Faster activation may be achieved by connecting a 1M
resistor between VBUS and GND. Reading from sub ad-
dress 0x07 has no effect on arming or activation and the
returned data is undefined, independent of the arming or
activation state.
Once engaged, ship-and-store mode can be disengaged
by applying power to the USB or WALL input or by writ-
ing any full data byte and acknowledge clock cycle to sub
address 0x06 if the I2C bus master is still powered.
I2C Interface
The LTC4156 may communicate with a bus master using
the standard I2C 2-wire interface. The Timing Diagram
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be HIGH when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required
on these lines. The LTC4156 is both a slave receiver and
slave transmitter. The I2C control signals, SDA and SCL,
are scaled internally to the DVCC supply. DVCC should be
connected to the same power supply as the bus pull-up
resistors.
The I2C port has an undervoltage lockout on the DVCC pin.
When DVCC is below approximately 1V, the I2C serial port
is cleared, the LTC4156 is set to its default configuration,
pending interrupts will be cleared, and future interrupts
will be disabled.
Bus Speed
The I2C port is designed to operate at speeds of up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I2C compliant master
device. It also contains input filters designed to suppress
glitches.
CHGSNS
LTC4156
BATGATE
BATSNS
+
4156 F04
Figure 4. Ship-and-Store Mode Required Components
to Enforce Downstream (VOUT) Shutdown
START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to
the LTC4156, the master may transmit a STOP condi-
tion which commands the LTC4156 to act upon its new
command set. A STOP condition is sent by the master by
transitioning SDA from LOW to HIGH while SCL is HIGH.
4156f
24
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