LTC4214-2IMS View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214-2IMS' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
2
GND – (–12V)
3 4 56 7 8 9 1011
UV/OV
VUVHI
VIN
VLKO
TIMER
5µA
VTMRH
40µA + 8 • IDRN
5µA
VTMRL
5µA
GATE
SS
VGATEL
SENSE
50µA
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
50µA
VIN – VGATEH
VACL
VCB
VOUT
DRAIN
VDRNCL
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F09
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
makes contact and its voltage exceeds VUVHI. In addition,
the internal logic checks for OV < VOVHI, GATE < VGATEL,
SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all
conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5µA current source pull-
up. At time point 3, TIMER reaches the VTMRH threshold
and the initial timing cycle terminates. The TIMER capaci-
tor is quickly discharged. At time point 4, the VTMRL
threshold is reached and the conditions of GATE < VGATEL,
SENSE < VCB and SS < 20 • VOS must be satisfied before
a GATE start-up cycle begins. SS ramps up as dictated by
RSS␣ •␣ CSS; GATE is held low by the analog current limit
amplifier until SS crosses 20 • VOS. Upon releasing GATE,
50µA sources into the external MOSFET gate and com-
pensation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
VACL(t) and soft-start limits the slew rate of the load
current. If the SENSE voltage (VSENSE – VEE) reaches the
VCB threshold at time point 7, the circuit breaker TIMER
activates. The TIMER capacitor, CT, is charged by a
421412f
21
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