LTC4214-1/LTC4214-2
PI FU CTIO S
UV (Pin 9): Undervoltage Input. The active high threshold
at the UV pin is set at 2.25V with respect to VEE and exhibits
0.25V hysteresis. If UV < 2V, PWRGD pulls high, both
GATE and TIMER pull low. If UV rises above 2.25V, this
initiates an initial timing cycle followed by GATE start-up.
The internal UVLO at VIN always overrides UV. A low at UV
resets an internal fault latch. A 1nF to 10nF capacitor at UV
prevents transients and switching noise from affecting the
UV thresholds and prevents glitches at the GATE pin.
TIMER (Pin 10): Timer Input. TIMER is used to generate
an initial timing delay at start-up and to delay shutdown in
the event of an output overload (circuit breaker fault).
TIMER starts an initial timing cycle when the following
conditions are met: UV is high, OV is low, VIN clears UVLO,
TIMER pin is low, GATE is lower than VGATEL, SS < 0.2V,
and VSENSE – VEE < VCB. A pull-up current of 5µA then
charges CT, generating a time delay. If CT charges to
VTMRH (3V), the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 40µA pull-up current charging
CT. If DRAIN is approximately 4.2V during this cycle, the
timer pull-up has an additional current of 8 • IDRN. If SENSE
drops below 50mV before TIMER reaches 3V, a 5µA pull-
down current slowly discharges the CT. In the event that CT
eventually integrates up to the VTMRH threshold, the circuit
breaker trips, GATE quickly pulls low and PWRGD pulls
high. The LTC4214-1 TIMER pin latches high with a 5µA
pull-up source. This latched fault is cleared by either
pulling TIMER low with an external device or by pulling UV
below 2V. The LTC4214-2 starts a shutdown cooling cycle
following an overcurrent fault. This cycle consists of 4
discharging ramps and 3 charging ramps. The charging
and discharging currents are 5µA and TIMER ramps
between its 1.7V and 3V thresholds. At the completion of
a shutdown cooling cycle, the LTC4214-2 attempts a start-
up cycle.
421412f
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