LTC4216CMS View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4216CMS' PDF : 24 Pages View PDF
LTC4216
Applications Information
For example, if C2 = 10nF, dVSS(NOM) = 1V/ms and
dt
dVSS(SLOW) = 0.1V/ms.
dt
After the initial timing cycle, the SS capacitor is charged
by a 10µA current source pull-up and GATE is held low
by the ACL amplifier. As SS ramps up, the ACL amplifier
releases the GATE when it crosses its input offset volt-
age. At this instant, SS switches the pull-up current from
10µA to 1µA for a slower ramp rate. GATE continues to
charge up with 20µA pull-up before the MOSFET reaches
its turn-on threshold voltage. When the external MOSFET
is first turned on, there is always a current step due to the
high gain of the MOSFET. The slower SS ramp rate allows
the gate of the external MOSFET to be turned on with a
smaller inrush current step.
When the external MOSFET is turned on, load current starts
to flow through the sense resistor, developing a voltage
drop across it. This allows the ACL amplifier to servo the
GATE to the voltage across the sense resistor, thus control-
ling the rate of change of the inrush current. At this instant,
SS switches back from 1µA to 10µA current source pull-up
for a normal ramp rate. GATE continues to ramp up as
the ACL amplifier servos to track the SS ramp rate. At the
end of SS ramp-up when SS reaches its final value, GATE
is servoed to ΔVACL(TH) across the sense resistor. If the
voltage across the sense resistor drops below ΔVACL(TH)
due to a falling load current, the ACL amplifier shuts off
and GATE ramps further by a 20µA pull-up.
SS is pulled low under any of the following conditions: in
VCC undervoltage lockout condition, during the first timing
cycle or when the circuit breaker fault times out. If the soft-
start function is not used, leave the SS pin unconnected.
rate by connecting an external capacitor, C4, from the GATE
pin to ground, as shown in Figure 7. An external resistor,
RG, of 10Ω prevents high frequency self-oscillations in
the MOSFET. The GATE slew rate is given by:
dVGATE = 20µA
dt C4 + CGATE
(7)
where CGATE is the associated parasitic GATE capacitance
due to the external MOSFET’s gate input capacitance, CISS.
The inrush current flowing into the load capacitor, CLOAD,
is limited to:
IINRUSH
=
C LOAD
•
dVGATE
dt
=
C LOAD
C4 + CGATE
• 20µA
(8)
For example, if CLOAD = 4700µF, C4 = 33nF and CGATE =
5nF, IINRUSH = 2.5A.
If CLOAD is very large and IINRUSH exceeds the analog
current limit, the GATE is servoed to control the inrush
current to ΔVACL(TH)/RSENSE.
One limitation with this technique is that it slows down
the system turn-on and turn-off time by adding a capaci-
tor at the GATE pin. Should this technique be used, C4 ≤
50nF is recommended. However, having an external gate
capacitor helps to eliminate voltage spikes coupled through
the MOSFET’s drain-to-gate capacitance to the GATE pin
when the supply power is first applied.
RSENSE
M1
VIN
RG
C4
+
VOUT
CLOAD
R4
Inrush Control with GATE Capacitor
For applications not requiring soft-start to control the di/dt
of the inrush current during power-up, an alternative way
to limit the inrush is to control the GATE pin voltage slew
SENSEP SENSEN GATE
FB
LTC4216**
R3
**ADDITIONAL DETAILS
OMITTED FOR CLARITY
4216 F07
Figure 7. Inrush Control with External Gate Capacitor
For more information www.linear.com/LTC4216
4216fa
13
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