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LTC4219IDHC-12 View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
LTC4219IDHC-12
Linear
Linear Technology Linear
'LTC4219IDHC-12' PDF : 18 Pages View PDF
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LTC4219
Applications Information
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci-
tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
Power Good Indication
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The LTC4219-12 and LTC4219-5 use an internal resis-
tive divider on the OUT pin to drive the FB pin. On the
LTC4219-12, the PG comparator indicates logic high when
OUT pin rises above 10.5V. If the OUT pin subsequently
falls below 10.3V, the comparator toggles low. On the
LTC4219-5 the PG comparator drives high when the OUT
pin rises above 4.35V and low when OUT falls below 4.27V.
Once the PG comparator is high, the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V, the PG pin goes low.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes high when the GATE is commanded off (using
the EN1, EN2 or SENSE pins) or when the PG comparator
drives low.
Design Example
Consider the following design example (Figure 5): VIN = 12V,
IMAX = 5A. IINRUSH = 100mA, CL = 330µF, VPGTHRESHOLD
= 10.5V.
The inrush current is defined by the current required to
charge the output capacitor using the fixed 0.3V/ms GATE
charge up rate. The inrush current is defined as:
IINRUSH = CL 0.3[V/ms] = 330µF 0.3[V/ms] = 100mA
As mentioned previously, the charge up time is the out-
put voltage (12V) divided by the output rate of 0.3V/ms
resulting in 40ms. The peak power dissipation of 12V at
100mA (or 1.2W) is within the SOA of the pass MOSFET
for 40ms (see MOSFET SOA curve in the Typical Perfor-
mance Characteristics section).
Next the power dissipated in the MOSFET during overcur-
rent must be limited. The active current limit uses a timer
to prevent excessive energy dissipation in the MOSFET.
The worst-case power dissipation occurs when the voltage
versus current profile of the foldback current limit is at the
maximum. This occurs when the current is 6.1A and the
voltage is one half of the VIN or 6V. See the Current Limit
Threshold Foldback vs FB Voltage in the Typical Perfor-
mance Characteristics section to view this profile. In order
to survive 36W, the MOSFET SOA dictates a maximum
time of 10ms (see SOA graph). Use the internal 2ms timer
invoked by tying the TIMER pin to INTVCC.
14
12V
VDD
OUT
Z1*
R3
200k
R2
200k
EN1
GATE
*TVS Z1: DIODES INC. SMAJ17A
EN2
R1
LTC4219DHC-12
10k
FLT
TIMER
INTVCC
C1
GND
1µF
PG
ISET
IMON
VOUT
12V
+ CL 5A
330µF
12V
R4
10k
PG = 10.5V
RMON
20k
ADC
4219 F05
Figure 5. 5A, 12V Card Resident Application
For more information www.linear.com/LTC4219
4219fd
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