LTC4220 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4220' PDF : 36 Pages View PDF
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Approximating a linear charging rate as IDRN drops from
IDRN(MAX) to zero, the IDRN component in Equation (3)
can be approximated with 0.5 • IDRN(MAX). Rearranging
equation, TIMER capacitor CT is given by:
( ) CT = tCL(CHARGE) •
230μA + 4 •IDRN(MAX)
4V
(13)
Returning to Equation (3), the TIMER period is calcu-
lated and used in conjunction with VSUPPLY(MAX) and
ISHORTCIRCUIT(MAX) to check the SOA curves of a prospec-
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If VSUPPLY(MAX)
= 72V and CL = 100μF, RD = 1MΩ, Equation (8) gives RS
= 40mΩ; Equation (13) gives CT = 441nF. To account for
errors in RS, CT, TIMER current (230μA), TIMER threshold
(4V), RD, DRAIN current multiplier and DRAIN voltage
clamp (VDRNCL), the calculated value should be multiplied
by 1.5, giving the nearest standard value of CT = 680nF.
If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A
will flow in the MOSFET for 5.6ms as dictated by CT = 680nF
in Equation (3). The MOSFET must be selected based on
this criterion. The IRF530S can handle 100V and 3A for
10ms and is safe to use in this application.
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
ICB(MAX)=
VCB(MAX)
RS
(14)
where VCB(MAX) = 60mV (55mV for the LTC4252A).
From the SOA curves of a prospective MOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
CSS
=
tSOA(MAX)
0.916 •RSS
(15)
In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX)
for the IRF530S is 40ms. From Equation (15), CSS =
437nF. Actual board evaluation showed that CSS = 100nF
was appropriate. The ratio (RSS • CSS) to tCL(CHARGE) is
a good gauge as a large ratio may result in the time-out
period expiring. This gauge is determined empirically with
board level evaluation.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2 with the LTC4252A. It was designed
for 80W.
Calculate the maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, IIN(MAX) = 2.2A.
Calculate RS: from Equation (8) RS = 20mΩ.
Calculate ISHORTCIRCUIT(MAX): from Equation (10)
ISHORTCIRCUIT(MAX)
=
66mV
20mΩ
=
3.3A
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate CT: from Equation (13) CT = 322nF. Select
CT = 680nF, which gives the circuit breaker time-out period
t = 5.6ms.
Consult MOSFET SOA curves: the IRF530S can handle 3.3A
at 100V for 8.2ms, so it is safe to use in this application.
Calculate CSS: using Equations (14) and (15) select
CSS = 68nF.
FREQUENCY COMPENSATION
The LTC4252A typical frequency compensation network for
the analog current limit loop is a series RC (10Ω) and CC
connected to VEE. Figure 7 depicts the relationship between
the compensation capacitor CC and the MOSFET’s CISS.
The line in Figure 7 is used to select a starting value for CC
based upon the MOSFET’s CISS specification. Optimized
values for CC are shown for several popular MOSFETs.
Differences in the optimized value of CC versus the starting
value are small. Nevertheless, compensation values should
be verified by board level short-circuit testing.
20
425212fd
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