LTC4306IGN View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4306IGN' PDF : 20 Pages View PDF
LTC4306
U
OPERATIO
SDA
a6-a0
d7-d0
d7-d0
SCL
S
1-7
8
9
1-7
8
9
1-7
8
9
P
START
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
Figure 3. Data Transfer Over I2C or SMBus
ACK
STOP
CONDITION
4306 F03
1
START
7
10 a4-a0
SLAVE
ADDRESS
1
1
8
1
WR ACK
XXXXXX r1r0
ACK
S
REGISTER
S
0
0
0
WRITE BYTE PROTOCOL
8
d7-d0
DATA
BYTE
1
1
ACK STOP
S
0
1
START
7
10 a4-a0
SLAVE
ADDRESS
1
1
WR ACK
S
0
0
8
XXXXXX r1r0
REGISTER
1
1
7
ACK START 10 a4-a0
S
SLAVE
0
ADDRESS
READ BYTE PROTOCOL
1
1
RD ACK
S
1
0
8
d7-d0
DATA
BYTE
1
1
ACK STOP
M
1
1
7
1
1
8
1
1
S
0001 100 RD ACK DEVICE ADDRESS ACK P
S
M
1
0
1
ALERT RESPONSE ADDRESS PROTOCOL
4306 F04
Figure 4. Protocols Accepted by LTC4306
is 35Ω, making the GPIO pull-downs capable of driving
LEDs. At VCC = 5V, the typical pull-up impedance is 320Ω
and the typical pull-down impedance is 20Ω. In open-
drain output mode, the user provides the logic high by
connecting a pull-up resistor between the GPIO pin and an
external supply voltage. The external supply voltage can
range from 1.5V to 5.5V independent of the VCC voltage.
In input mode, the GPIO input threshold voltage is 1V.
The GPIO1 and GPIO2 Logic State bits in register 1
indicate the logic state of the two GPIO pins. The logic-
level threshold voltage for each pin is 1V. The GPIO1 and
GPIO2 Output Driver State bits in register 1 indicate the
logic state that the LTC4306 is attempting to write to the
GPIO pins. This is useful when the GPIOs are being used
in open-drain output mode and one or more external
devices are connected to the GPIOs. If the LTC4306 is
trying to write a high to a GPIO pin, but the pin’s actual
logic state is low, then the LTC4306 knows that the low is
being forced by an external device.
Glitch Filters
The LTC4306 provides glitch filters on the SDAIN and
SCLIN pins as required by the I2C Fast Mode (400kHz)
Specification. The filters prevent signals of up to 50ns
(minimum) time duration and rail-to-rail voltage
magnitude from passing into the two-wire bus digital
interface circuitry.
4306f
14
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