LTC4309
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
0.70 p0.05
3.60 p0.05
1.70 p0.05
2.20 p0.05 (2 SIDES)
PACKAGE OUTLINE
0.25 p 0.05
0.50
BSC
3.30 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 p0.10
(2 SIDES)
R = 0.05
TYP
R = 0.115
7
TYP
0.40 p 0.10
12
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 p0.10 1.70 p 0.05
(2 SIDES) (2 SIDES)
0.75 p0.05
0.00 – 0.05
6
1
0.25 p 0.05
0.50
BSC
3.30 p0.05
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
(UE12/DE12) DFN 0905 REV C
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.254 MIN
.045 p.005
.150 – .165
.189 – .196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
.009
(0.229)
REF
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.0165 p.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.007 – .0098
(0.178 – 0.249)
.015 p .004
(0.38 p 0.10)
s
45o
0o – 8o TYP
1 234 5678
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2.
DIMENSIONS
ARE
IN
INCHES
(MILLIMETERS)
3. DRAWING NOT TO SCALE
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0204
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
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