LTC5599IUFPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5599IUFPBF' PDF : 42 Pages View PDF
LTC5599
Applications Information
SPI Signal Levels
The SPI bus supports signal levels from a digital VCC_L
from 1.2V to 3.6V. The CSB = 1.2V condition creates an
additional static input sleep current of 0.2µA. For CSB =
1.8V the extra sleep current can be neglected.
Evaluation Board
Figure 13 shows the evaluation board schematic. A good
ground connection is required for the exposed pad. If this
is not done properly, the RF performance will degrade.
Figures 14 and 15 show the component side and bottom
side of the evaluation board.
Ferrite bead FB1 limits the supply voltage ramping speed
in case VCC is abruptly connected to a voltage source. In
the application, limit the VCC ramp speed to a maximum
of 1V/µs.
VCC_L
1.2V TO 3.6V
FB1
FERRITE BEAD
TDK, MPZ1608S331AT
VCC
2.7V TO 3.6V
C1
4.7µF
C17
100nF
R18 (RPULL-UP)
1k
C2
1nF
EN
R1, 1Ω
VCTRL
C3
100nF
LO
TTCK
L1, 39nH
C5, 15pF
25 24 23 22 21 20 19
GND VCC EN SDO SDI SCLK CSB
1 VCTRL
2 GND
3 LOL
4 LOC
5 GND
6 TTCK
LTC5599IUF
GNDRF 18
GNDRF 17
RF 16
GNDRF 15
GNDRF 14
GNDRF 13
R19, 1k
R26, 1k
R25, 1k
C18
2.2pF
C13
2.2pF
C12
2.2pF
R23, 1k
C10
2.2pF
C4
10nF
RF
SDO
SDI
SCLK
CSB
TEMP
BBPI
TEMP BBPI BBMI BBPQ BBMQ GND
7 8 9 10 11 12
BBPQ
BBPQ
R9
49.9Ω
C7
100nF
R8
49.9Ω
C6
100nF
BOARD NUMBER: DC2091A
R10
49.9Ω
C8
100nF
R11
49.9Ω
C9
100nF
BBMQ
5599 F13
Figure 13. Evaluation Circuit Schematic
For more information www.linear.com/LTC5599
5599f
31
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