LTC5800-IPR View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5800-IPR' PDF : 28 Pages View PDF
Advanced Information
hardware-based autonomous MAC that handles precise sequencing of peripherals, including the transmitter, the receiver, and
AES peripherals. The hardware-based autonomous MAC minimizes CPU activity, thereby further decreasing power
consumption.
2.5
UARTs
The principal network interface is through the application programming interface (API) UART. A command-line interface
(CLI) is also provided for support of test and debug functions. Both UARTs sense activity continuously, consuming virtually
no power until data is transferred over the port and then automatically returning to their lowest power state after the
conclusion of a transfer.
2.5.2
API UART Protocol
Eterna’s API UART operates in Mode 4, incorporating optional flow control, at 115200 baud. Packets are HDLC encoded
with one stop bit and no parity bits. The flow control signals for Eterna’s API receive path are shown in Figure 5. If the flow
control signals are used (recommended) transfers are initiated from a companion processor by asserting UART_RX_RTSn.
Eterna responds by asserting UART_RX_CTSn. If flow control is used, after detecting the assertion of UART_RX_CTSn the
companion processor may send the entire packet. Following the transmission of the final byte in the packet the companion
processor negates UART_RX_RTSn and waits until the negation of UART_RX_CTSn before asserting UART_RX_RTSn
again. Flow control automatically ensures compliance with inter-packet delay requirements, so explicit delay-checking is not
required.
If flow control is not desired or needed it may be disabled by tying UART_RX_RTSn high. When flow control is not used
the companion processor may send the entire packet; in this case the companion processor must comply with the minimum
inter-packet delay as defined in section 8.9.
Figure 5 UART Mode 4 Receive Flow Control
UART Mode 4 also incorporates level-sensitive flow control for Eterna UART transmissions on the UART TX pin. Packets
are HDLC encoded with one stop bit and no parity bits. The flow control signals for TX are shown in Figure 6. A transfer
request is signaled by Eterna device asserting UART_TX_RTSn. The UART_TX_CTSn signal may be actively driven by the
companion processor when it is ready to receive a packet or it may be tied low if the companion processor will always be
ready to receive a packet. After detecting a logic ‘0’ on UART_TX_CTSn Eterna sends the entire packet. Following the
transmission of the final byte in the packet Eterna negates UART_TX_RTSn and waits for a minimum period (what is the
period called?) defined in section 8.9 before asserting UART_TX_RTSn again (if a packet needs to be transmitted)
Eterna Datasheet
Linear Technology / Dust Networks
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