LTC6803-2 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC6803-2' PDF : 40 Pages View PDF
LTC6803-2/LTC6803-4
OPERATION
Data Link Layer
Clock Phase And Polarity: The LTC6803 SPI compat-
ible interface is configured to operate in a system using
CPHA = 1 and CPOL = 1. Consequently, data on SDI must
be stable during the rising edge of SCKI.
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 2). Similarly, on a read, the
data value output on SDO is valid during the rising edge of
SCKI and transitions on the falling edge of SCKI (Figure 3).
CSBI must remain low for the entire duration of a com-
mand sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
Network Layer
PEC Byte: The packet error code (PEC) byte is a cyclic
redundancy check (CRC) value calculated for all of the
bits in a register group in the order they are passed, us-
ing the initial PEC value of 01000001 and the following
characteristic polynomial:
x8 + x2 + x + 1
To calculate the 8-bit PEC value, a simple procedure can
be established:
1. Initialize the PEC to 0100 0001.
2. For each bit DIN coming into the register group, set IN0
= DIN XOR PEC[7], then IN1 = PEC[0] XOR IN0, IN2 =
PEC[1] XOR IN0.
3. Update the 8-bit PEC as PEC[7] = PEC[6], PEC[6] =
PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2, PEC[1]
= IN1, PEC[0] = IN0.
4. Go back to step 2 until all data are shifted. The 8-bit
result is the final PEC byte.
CSBI
SCKI
SDI
CSBI
SCKI
SDI
SDO
MSB (CMD) BIT 6 (CMD)
LSB (CMD) MSB (DATA)
Figure 2. Transmission Format (Write)
MSB (CMD) BIT 6 (CMD)
LSB (CMD)
MSB (DATA)
Figure 3. Transmission Format (Read)
LSB (DATA)
68034 F02
LSB (DATA)
68034 F03
680324f
17
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