LTC6908-1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC6908-1' PDF : 16 Pages View PDF
LTC6908-1/LTC6908-2
PI FU CTIO S (DCB Package/S6 Package)
SET (Pin 1/Pin 3): Frequency-Setting Resistor Input. The
value of the resistor connected between this pin and V+
determines the oscillator frequency. The voltage on this pin
is held by the LTC6908 to approximately 1.1V below the
V+ voltage. For best performance, use a precision metal
film resistor with a value between 20k and 400k and limit
the capacitance on this pin to less than 10pF.
V+ (Pin 2/Pin 1): Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This
supply must be kept free from noise and ripple. It should
be bypassed directly to a ground plane with a 0.1µF
capacitor.
GND (Pin 3/Pin 2): Ground. Should be tied to a ground
plane for best performance.
OUT1 (Pin 4/Pin 6), OUT2 (Pin 5/Pin 5): Oscillator Out-
puts. These pins can drive 5k and/or 10pF loads. Larger
loads may cause inaccuracies due to supply bounce at
high frequencies.
MOD (Pin 6/Pin 4): Modulation-Setting Input. This three-
state input selects among four modulation rate settings.
The MOD pin should be tied to ground for the fOUT/16
modulation rate. Floating the MOD pin selects the fOUT/32
modulation rate. The MOD pin should be tied to V+ for the
fOUT/64 modulation rate. Tying one of the outputs to the
MOD pin turns the modulation off. To detect a floating
MOD pin, the LTC6908 attempts to pull the pin toward
midsupply. This is realized with two internal current
sources, one tied to V+ and MOD and the other one tied
to ground and MOD. Therefore, driving the MOD pin high
requires sourcing approximately 2µA. Likewise, driving the
MOD pin low requires sinking 2µA. When the MOD pin is
floated, it must be bypassed by a 1nF capacitor to ground.
Any AC signal coupling to the MOD pin could potentially
be detected and stop the frequency modulation.
Exposed Pad (Pin 7/NA): Ground. The Exposed Pad must
be soldered to PCB.
BLOCK DIAGRA (S6 Package Pin Numbers)
V+
1
RSET
3
SET
VBIAS
fMASTER
=
20MHz
•
10k
•
IMASTER
V+ – V(SET)
=
20MHz
•
10k/RSET
fOUT = fMASTER/2
+
GAIN = 1
V+ – V(SET) ≈ 1.13V
–
V+ – V(SET)
ISET = RSET
1-POLE
LPF
MASTER
OSCILLATOR
V
OUT
IMASTER
COMPLEMENTARY
OR
QUADRATURE
OUTPUTS
0
90/180
6 OUT1
5 OUT2
V+
–+
2µA
MOD 4
–+
2µA
GND
IREF
MDAC
MUTE OUTPUT
UNTIL STABLE
POR
PSEUDO RANDOM
CODE GENERATOR
CLK
3-STATE
INPUT DECODER
DIVIDER SELECT
DIVIDE BY
16/32/64
DETECT
CLOCK INPUT
WHEN A CLOCK SIGNAL IS PRESENT AT THE
MOD INPUT, DISABLE THE MODULATION.
2 GND
6
690812 BD
690812fa
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