LTC6909 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC6909
Linear Technology
'LTC6909' PDF : 20 Pages View PDF
BLOCK DIAGRAM
V+A
1
RSET
16
SET
VSET
VBIAS
+
–
ISET
=
V+ – VSET
RSET
PH0 PH1 PH2
3 4 15
fMASTER = 20MHz • 10k •
(SSFM = OFF)
IMASTER
V+ – VSET
= 20MHz • 10k/RSET
MASTER
OSCILLATOR
V
OUT
1 POLE
LPF
IMASTER
OUTPUT
PHASING
DRIVERS
IREF
MDAC
V+
–+
MOD 14
GND 2
–+
GND
PSEUDORANDOM
CODE GENERATOR
POR
3-STATE
INPUT DECODER
DETECT
WHEN A CLOCK SIGNAL IS PRESENT AT THE
CLOCK INPUT MOD PIN INPUT, THE MODULATION IS DISABLED
OUTPUT
Hi-Z
UNTIL
STABLE
DIVIDE BY
16/32/64
LTC6909
V+D
13
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
5 OUT1
6 OUT2
7 OUT3
8 OUT4
9 OUT5
10 OUT6
11 OUT7
12 OUT8
6909 BD
6909f
7
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