LTC6948-1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC6948-1
Linear Technology
'LTC6948-1' PDF : 36 Pages View PDF
LTC6948
Operation
Block Power-Down Control
The LTC6948’s power-down control bits are located in
register h02, described in Table 16. Different portions of
the device may be powered down independently. Care must
be taken with the LSB of the register, the POR (power-on-
reset) bit. When written to a 1, this bit forces a full reset
of the part’s digital circuitry to its power-up default state.
Table 16. Serial Port Register Bit Field Summary
BITS DESCRIPTION
ALCCAL Auto Enable ALC During CAL Operation
ALCEN Always Enable ALC (Override)
ALCHI ALC too Hi Flag
ALCLO ALC too Low Flag
ALCMON Enable ALC Monitor for Status Flags Only
ALCULOK Enable ALC When PLL Unlocked
AUTOCAL Calibrate VCOs Whenever Registers h06 to
h0A Are Written
AUTORST Reset Modulator Whenever Registers h05
to h0A Are Written
BD[3:0] Calibration B Divider Value
BST REF Buffer Boost Current
CAL Start VCO Calibration (Auto Clears)
CP[2:0] CP Output Current
CPCHI Enable Hi-Voltage CP Output Clamp
CPCLO Enable Low-Voltage CP Output Clamp
CPDN Force CP Pump Down
CPINV Invert CP Phase
CPLE CP Linearizer Enable
CPMID CP Bias to Mid-Rail
CPRST CP Tri-State
CPUP Force CP Pump Up
CPWIDE Extend CP Pulse Width
DITHEN Enable Fractional Numerator Dither
FILT[1:0] REF Input Buffer Filter
INTN Integer Mode; Fractional Modulator Placed
in Standby
DEFAULT
1
1
0
0
1
1
h3
1
0
h7
1
1
0
0
0
1
1
0
0
1
h3
0
BITS DESCRIPTION
LDOEN LDO Enable
LDOV[1:0] LDO Voltage
LKCT[1:0] PLL Lock Cycle Count
LKWIN[2:0] PLL Lock Indicator Window
LOCK PLL Lock Indicator Flag
MTCAL Mute RF Output During Calibration
ND[9:0] N Divider Value (ND[9:0] ≥ 32)
NUM[17:0] Fractional Numerator Value
OD[2:0] Output Divider Value (0 < OD[2:0] < 7)
OMUTE Mutes RF Output
PART[3:0] Part Code (h01 for -1, h02 for -2, h03 for
-3, h04 for -4 version)
PDALL Full Chip Powerdown
PDFN Powers Down LDO and Modulator Clock
PDOUT Powers Down O_DIV, RF Output Buffer
PDPLL Powers Down REF, R_DIV, PFD, CPUMP,
N_DIV
PDVCO Powers Down VCO, N_DIV
POR Force Power-On-Reset
RD[4:0] R Divider Value (RD[4:0] > 0)
REV[3:0] Rev Code
RFO[1:0] RF Output Power
RSTFN Force Modulator Reset (Auto Clears)
SEED[7:0] Modulator Dither Seed Value
THI CP Clamp High Flag
TLO CP Clamp Low Flag
UNLOK PLL Unlock Flag
x[5:0] STAT Output OR Mask
DEFAULT
1
h3
h1
h2
1
h0FA
h3FFF
h1
1
h01, h02,
h03, h04
0
0
0
0
0
0
h001
h1
h3
0
h11
h04
6948f
24
For more information www.linear.com/LTC6948
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