LTC6948-3 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC6948-3
Linear Technology
'LTC6948-3' PDF : 36 Pages View PDF
LTC6948
Applications Information
Introduction
A PLL is a complex feedback system that may conceptu-
ally be considered a frequency multiplier. The system
multiplies the frequency input at REF± and outputs a higher
frequency at RF±. The PFD, charge pump, N divider, VCO
and external loop filter form a feedback loop to accurately
control the output frequency (see Figure 13).
The external loop filter is used to set the PLL’s loop
bandwidth BW. Lower bandwidths generally have better
spurious performance and lower Δ∑ modulator quantization
noise. Higher bandwidths can have better total integrated
phase noise.
The R and O divider and input frequency fREF are used to
set the output frequency resolution. When in fractional
mode, the Δ∑ modulator changes the N divider’s ratio
each PFD cycle to produce an average fractional divide
ratio. This achieves a much smaller frequency resolution
for a given fPFD as compared to integer mode.
Output Frequency
When the loop is locked, the frequency fVCO (in Hz)
produced at the output of the VCO is determined by the
reference frequency fREF, the R and N divider values, and
the fractional value F, given by Equation 3:
fVCO
=
fREF
• (N + F)
R
(3)
where the fractional value F is given by Equation 4:
F
=
NUM
218
(4)
NUM is programmable from 1 to 262143, or 218 – 1. When
using the LTC6948 in integer mode, F = 0.
The PFD frequency fPFD is given by the following equation:
fPFD
=
fREF
R
(5)
and fVCO may be alternatively expressed as:
fVCO = fPFD • (N + F)
(6)
The output frequency fRF produced at the output of the O
divider is given by Equation 7:
fRF
=
fVCO
O
(7)
Using the above equations, the minimum output frequency
resolution fSTEP(MIN) produced by a unit change in the
fractional numerator NUM while in fractional mode is
given by Equation 8:
fSTEP(MIN)
=
R
•
fREF
O • 218
(8)
LTC6948
REF±
(fREF)
R_DIV
÷R
fPFD KPFD
÷(N + F)
N_DIV
ICP CP
26
∆∑
RF±
TUNE
O_DIV
15
(fRF)
÷O
fVCO KVCO
LOOP FILTER
(FOURTH ORDER)
L1
C2
R1
RZ
CI
LF(s)
Figure 13. PLL Loop Diagram
CP
6948 F13
For more information www.linear.com/LTC6948
6948f
25
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