LTC6948IUFD-1TRPBF View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC6948IUFD-1TRPBF

Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO

Linear Technology 

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LTC6948

Applications Information

Using an ICP of 5.6mA, the FracNWizard uses Equation 12

to determine RZ:

RZ

=

2•π•

5.6m

150k • 76

• 220.4M

RZ = 58.0Ω

For the 4th order Filter 3, FracNWizard uses modified

Equations 13 and 14 to calculate CI, CP:

CI

=

2

•

π

•

4.5

150k

•

58

=

82.3nF

CP

=

10.5

•

π

1

• 150k

•

58

=

3.5nF

FracNWizard calculates R1, L1, and C2 to be:

R1 = 58.0Ω

C2 = 2.3nF

L1 = 7.8uH

Status Output Programming

This example will use the STAT pin to alert the system

whenever the LTC6948 generates a fault condition. Pro-

gram x[5], x[4], x[3], x[1], x[0] = 1 to force the STAT pin

high whenever any of the UNLOCK, ALCHI, ALCLO, THI,

or TLO flags asserts:

Reg01 = h3B

Power Register Programming

For correct PLL operation all internal blocks should be

enabled. OMUTE may remain asserted (or the MUTE pin

held low) until programming is complete. For OMUTE = 1:

Reg02 = h02

VCO ALC, AUTOCAL, and AUTORST Programming

Set the ALC options (ALCMON = ALCULOK = ALCCAL = 1),

the auto reset options (AUTOCAL = AUTORST = 1), and

the Δ∑ modulator modes (DITHEN = 1, INTN = 0) at the

same time:

Reg03 = h7E

The ALC will only be active during a calibration cycle or

when the loop is unlocked, but the ALCHI and ALCLO status

conditions will be monitored continuously. The VCO will

be calibrated and the Δ∑ modulator will be reset at the

end of the SPI write communication burst (assuming an

auto-increment write is used to write all registers).

LDO Programming

Use Table 13 and fPFD = 50MHz to determine V(LDO) and

LDOV[1:0]:

V(LDO) = 2.3V and LDOV[1:0] = 2

Use LDOV[1:0], LDOEN = 1 to enable the LDO, and the

previously determined BD[3:0] value to set Reg04. CPLE

should be set to 1 to reduce in-band noise and spurious

due to the Δ∑ modulator:

Reg04 = h5E

SEED Programming

The SEED[7:0] value is used to initialize the Δ∑ modulator

dither circuitry. Use the default value:

Reg05 = h11

R and N Divider and Numerator Programming

Program registers Reg06 to Reg0A with the previously

determined R and N divider and numerator values. Because

the AUTORST and AUTOCAL bits were previously set to

1, CAL and RSTFN do not need to be set:

Reg06 = h10

Reg07 = h4C

Reg08 = h37

Reg09 = h6C

Reg0A = h90

6948f

28

For more information www.linear.com/LTC6948

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