LTC6948IUFD-3 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC6948IUFD-3
Linear Technology
'LTC6948IUFD-3' PDF : 36 Pages View PDF
LTC6948
Operation
LDO Regulator
The adjustable low dropout (LDO) regulator supplies power
to the Δ∑ modulator. The regulator requires a low ESR
ceramic capacitor (ESR < 0.8Ω) connected to the LDO pin
(pin 7) for stability. The capacitor value may range from
0.047µF to 1µF.
The LDO voltage is set using the LDOV[1:0] bits, and should
be chosen based upon the fPFD frequency to minimize
power and spurious. The regulator is disabled by setting
the LDOEN bit to 0. When disabled by using either the
LDOEN or PDFN bits, the LDO pin is connected directly
to VD+ using a low impedance switch, and the regulator
is powered down. See Table 13 for programming details.
Table 13. LDOV[1:0] and LDOEN Programming
LDOV[1:0]
LDOEN
VLDO
0
1
1.7V
1
1
2.0V
2
1
2.3V
3
1
2.6V
X
0
VD+
fPFD
≤34.3MHz
≤45.9MHz
≤56.1MHz
≤66.3MHz
≤76.1MHz
be combined externally, or used individually. Terminate
any unused output with a 50Ω resistor to VRF+.
Table 14. RFO[1:0] Programming
RFO[1:0}
0
PRF (DIFFERENTIAL)
–4.3dBm
1
–1.5dBm
2
1.6dBm
3
4.5dBm
PRF (SINGLE-ENDED)
–7.3dBm
–4.5dBm
–1.4dBm
1.5dBm
Each output is open-collector with 136Ω pull-up resistors
to VRF+, easing impedance matching at high frequencies.
See Figure 5 for circuit details and the Applications Infor-
mation section for matching guidelines. The buffer may be
muted with either the OMUTE bit, found in register h02,
or by forcing the MUTE input low.
VRF+
VRF+
136Ω
136Ω
RF+
12
RF– 11
Output (O) Divider
The 3-bit O divider can reduce the frequency from the VCO
to extend the output frequency range. Its divide ratio O
may be set to any integer from 1 to 6, inclusive, outputting
a 50% duty cycle even with odd divide values. Use the
OD[2:0] bits found in register h0B to directly program the
O divide ratio. See the Applications Information section
for the relationship between O and the fREF, fPFD, fVCO,
and fRF frequencies.
RF Output Buffer
The low noise, differential output buffer produces a dif-
ferential output power of –4.3dBm to +4.5dBm, settable
with bits RFO[1:0] according to Table 14. The outputs may
9 MUTE
OMUTE
MUTE
RFO[1:0]
6948 F05
Figure 5. Simplified RF Interface Schematic
Serial Port
The SPI-compatible serial port provides control and
monitoring functionality. A configurable status output
STAT gives additional instant monitoring.
Communication Sequence
The serial bus is comprised of CS, SCLK, SDI, and SDO.
Data transfers to the part are accomplished by the se-
rial bus master device first taking CS low to enable the
LTC6948’s port. Input data applied on SDI is clocked on
6948f
20
For more information www.linear.com/LTC6948
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