LTC6948IUFD-3PBF View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC6948IUFD-3PBF

Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO

Linear Technology 

Prev 21 22 23 24 25 26 27 28 29 30 Next

LTC6948

Applications Information

Reference Input Settings and Output Divider

Programming

From Table 1, FILT = 0 for a 100MHz reference frequency.

Next, convert 7dBm into VP–P. For a CW tone, use the

following equation with R = 50:

VP-P ≅ R • 10(dBm –21)/20

(15)

This gives VP-P = 1.41V, and, according to Table 2, set

BST = 1.

Now program Reg0B, assuming maximum RF± output

power (RFO[1:0] = 3 according to Table 14) and OD[2:0] = 2:

Reg0B = h9A

Lock Detect and Charge Pump Current Programming

Next, determine the lock indicator window from fPFD. From

Table 3 we see that LKWIN[1:0] = 0 with a tLWW of 5ns for

CPLE = 1 and fVCO = 3.843GHz. The LTC6948 will consider

the loop locked as long as the phase coincidence at the

PFD is within 90°, as calculated below.

phase = 360° • tLWW • fPFD = 360 • 5n • 50M

= 90°

Choosing the correct COUNTS value depends upon the

OSR. Smaller ratios dictate larger COUNTS values, although

application requirements will vary. A COUNTS value of 32

will work for the OSR of 333. From Table 5, LKCT[1:0] = 1

for 32 counts.

Using Table 6 with the previously selected ICP of 5.6mA

gives CP[3:0] = 7. This gives enough information to pro-

gram Reg0C:

Reg0C = h0D

Charge Pump Function Programming

This example uses the additional voltage clamp features

to allow the monitoring of fault conditions by setting

CPCHI = 1 and CPCLO = 1. If something occurs and the

system can no longer lock to its intended frequency, the

charge pump output will move toward either GND or

VCP+, thereby setting either the TLO or THI status flags,

respectively. Disable all the other charge pump functions

(CPMID, CPINV, CPRST, CPUP, and CPDN), allowing the

loop to lock:

Reg0D = hC0

The loop should now lock. Now un-mute the output by

setting OMUTE = 0 (assumes the MUTE pin is high).

Reg02 = h04

Reference Source Considerations

A high quality signal must be applied to the REF± inputs as

they provide the frequency reference to the entire PLL. As

mentioned previously, to achieve the part’s in-band phase

noise performance, apply a CW signal of at least 6dBm

into 50Ω, or a square wave of at least 0.5VP-P with slew

rate of at least 40V/µs.

The LTC6948 may be driven single-ended to CMOS levels

(greater than 2.7VP-P ). Apply the reference signal at REF+,

and bypass REF– to GND with a 47pF capacitor. The BST

bit must also be set to 0, according to guidelines given

in Table 2.

The LTC6948 achieves an integer mode in-band normalized

phase noise floor LNORM(INT) = –226dBc/Hz typical, and

a fractional mode phase noise floor LNORM(FRAC) = –225

dBc/Hz typical. To calculate its equivalent input phase

noise floor LIN, use the following Equation 16.

LIN = LNORM + 10 • log10 (fREF)

(16)

For example, using a 10MHz reference frequency in integer

mode gives an input phase noise floor of –156dBc/Hz.

The reference frequency source’s phase noise must be at

least 3dB better than this to prevent limiting the overall

system performance.

For more information www.linear.com/LTC6948

6948f

29

Share Link: