LTC6948IUFD-4PBF View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC6948IUFD-4PBF

Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO

Linear Technology 

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LTC6948

Operation

The LTC6948 is a high-performance fractional-N PLL

complete with a low noise VCO available in four different

frequency range options. The output frequency range

may be further extended by utilizing the output divider

(see Available Options table for more details). The device

is able to achieve superior integrated phase noise by the

combination of its extremely low in-band phase noise

performance and excellent VCO noise characteristics.

The fractional-N feedback divider uses an advanced Δ∑

modulator, resulting in virtually no discrete modulator

spurious tones. The modulator may be disabled if integer-N

feedback is required.

Reference Input Buffer

The PLL’s reference frequency is applied differentially on

pins REF+ and REF–. These high impedance inputs are

self-biased and must be AC-coupled with 1µF capacitors

(see Figure 1 for a simplified schematic). Alternatively, the

inputs may be used single-ended by applying the refer-

ence frequency at REF+ and bypassing REF– to GND with

a 1µF capacitor. If the single-ended signal is greater than

2.7VP-P, then use a 47pF capacitor for the GND bypass.

BIAS

1.9V

VREF+

VREF+

LOWPASS

4.2k 4.2k

REF+

1

FILT[1:0]

REF–

28

6948 F01

BST

Figure 1. Simplified REF Interface Schematic

A high quality signal must be applied to the REF± inputs

as they provide the frequency reference to the entire PLL.

To achieve the part’s in-band phase noise performance,

apply a CW signal of at least 6dBm into 50Ω, or a square

wave of at least 0.5VP-P with slew rate of at least 40V/µs.

Additional options are available through serial port register

h0B to further refine the application. Bits FILT[1:0] control

the reference input buffer’s lowpass filter, and should be

set based upon fREF to limit the reference’s wideband

noise. The FILT[1:0] bits must be set correctly to reach the

LNORM normalized in-band phase noise floor. See Table 1

for recommended settings.

Table 1. FILT[1:0] Programming

FILT[1:0]

3

2

1

0

fREF

<20MHz

NA

20MHz to 50MHz

>50MHz

The BST bit should be set based upon the input signal level

to prevent the reference input buffer from saturating. See

Table 2 for recommended settings and the Applications

Information section for programming examples.

Table 2. BST Programming

BST

1

0

VREF

<2VP-P

≥2VP-P

Reference (R) Divider

A 5-bit divider, R_DIV, is used to reduce the frequency

seen at the PFD. Its divide ratio R may be set to any inte-

ger from 1 to 31, inclusive. Use the RD[4:0] bits found in

registers h06 to directly program the R divide ratio. See

the Applications Information section for the relationship

between R and the fREF, fPFD, fVCO, and fRF frequencies.

Phase/Frequency Detector (PFD)

The phase/frequency detector (PFD), in conjunction with

the charge pump, produces source and sink current pulses

proportional to the phase difference between the outputs

of the R and N dividers. This action provides the necessary

feedback to phase-lock the loop, forcing a phase align-

6948f

14

For more information www.linear.com/LTC6948

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