LTM4601A View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTM4601A

12A DC/DC µModules with PLL, Output Tracking and Margining

Linear Technology 

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LTM4601A/LTM4601A-1

PIN FUNCTIONS (See Package Description for Pin Assignment)

VIN (Bank 1): Power Input Pins. Apply input voltage be-

tween these pins and PGND pins. Recommend placing

input decoupling capacitance directly between VIN pins

and PGND pins.

VOUT (Bank 3): Power Output Pins. Apply output load

between these pins and PGND pins. Recommend placing

output decoupling capacitance directly between these pins

and PGND pins. Review the figure below.

PGND (Bank 2): Power ground pins for both input and

output returns.

VOSNS– (Pin M12): (–) Input to the Remote Sense Amplifier.

This pin connects to the ground remote sense point. The

remote sense amplifier is used for VOUT ≤3.3V.

NC1 (Pin M12): No Connect On the LTM4601A-1.

VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifier.

This pin connects to the output remote sense point. The

remote sense amplifier is used for VOUT ≤3.3V.

NC2 (Pin J12): No Connect On the LTM4601A-1.

DIFFVOUT (Pin K12): Output of the Remote Sense Ampli-

fier. This pin connects to the VOUT_LCL pin.

NC3 (Pin K12): No Connect On the LTM4601A-1.

DRVCC (Pin E12): This pin normally connects to INTVCC

for powering the internal MOSFET drivers. This pin can

be biased up to 6V from an external supply with about

50mA capability, or an external circuit shown in Figure 16.

This improves efficiency at the higher input voltages by

reducing power dissipation in the module.

TOP VIEW

A

VIN B

BANK 1 C

MTP1

fSET

MARG0

D

E

F

PGND

BANK 2 G

H

J

VOUT

BANK 3

K

L

M

INTVCC MTP2

MTP3

MARG1

DRVCC

VFB

PGOOD

SGND

VOSNS+/NC2*

DIFFVOUT/NC3*

VOUT_LCL

VOSNS–/NC1*

1 2 3 4 5 6 7 8 9 10 11 12

*LTM4601A-1 ONLY

INTVCC (Pin A7, D9): This pin is for additional decoupling

of the 5V internal regulator. These pins are internally

connected. Pin A7 is a test pin.

PLLIN (Pin A8): External Clock Synchronization Input to

the Phase Detector. This pin is internally terminated to

SGND with a 50k resistor. Apply a clock above 2V and

below INTVCC. See Applications Information.

TRACK/SS (Pin A9): Output Voltage Tracking and Soft-

Start Pin. When the module is configured as a master

output, then a soft-start capacitor is placed on this pin

to ground to control the master ramp rate. A soft-start

capacitor can be used for soft-start turn on as a stand

alone regulator. Slave operation is performed by putting

a resistor divider from the master output to the ground,

and connecting the center point of the divider to this pin.

See Applications Information.

MPGM (Pins A12, B11): Programmable Margining Input.

A resistor from this pin to ground sets a current that is

equal to 1.18V/R. This current multiplied by 10kΩ will

equal a value in millivolts that is a percentage of the 0.6V

reference voltage. See Applications Information. To parallel

LTM4601As, each requires an individual MPGM resistor.

Do not tie MPGM pins together. Both pins are internally

connected. Pin A12 is a test pin.

fSET (Pins B12, C11): Frequency Set Internally to 850kHz.

An external resistor can be placed from this pin to ground

to increase frequency. This pin can be decoupled with a

1000pF capacitor. See Applications Information for fre-

quency adjustment. Both pins are internally connected.

Pin B12 is a test pin.

VFB (Pin F12): The Negative Input of the Error Amplifier.

Internally, this pin is connected to VOUT_LCL pin with a

60.4k precision resistor. Different output voltages can be

programmed with an additional resistor between VFB and

SGND pins. See Applications Information.

MARG0 (Pin C12): This pin is the LSB logic input for the

margining function. Together with the MARG1 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See Applications Information.

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