LTM4601AV-1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTM4601AV-1' PDF : 28 Pages View PDF
LTM4601A/LTM4601A-1
APPLICATIONS INFORMATION
Solution
Lower the switching frequency at lower input voltages
to allow for higher duty cycles, and meet the 400ns
minimum off time at 4.5V input voltage. The off time
should be about 500ns with 100ns guard band. The duty
cycle for (3.3V/4.5) ≈ 73%. Frequency = (1 – DC)/tOFF, or
(1 – 0.73)/500ns = 540kHz. The switching frequency needs
to be lowered to 540kHz at 4.5V input. tON = DC/frequency,
or 1.35μs. The fSET pin voltage compliance is 1/3 of VIN, and
the IfSET current equates to 38μA with the internal 39.2k.
The IfSET current needs to be 24μA for 540kHz operation.
A resistor can be placed from VOUT to fSET to lower the
effective IfSET current out of the fSET pin to 24μA. The fSET
pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore 130k will
source 14μA into the fSET node and lower the IfSET cur-
rent to 24μA. This enables the 540kHz operation and the
4.5V to 20V input operation for down converting to 3.3V
output. The frequency will scale from 540kHz to 1.1MHz
over this input range. This provides for an effective output
current of 8A over the input range.
VIN
10V TO 20V
C2
10μF
25V
VOUT
R2 R4
100k 100k
5% MARGIN
R1
392k
1%
C1
10μF
25V
TRACK/SS CONTROL
VIN
PGOOD
PLLIN TRACK/SS
VOUT
MPGM
RUN
VFB
MARG0
COMP
INTVCC
DRVCC
LTM4601A-1 MARG1
VOUT_LCL
NC3
NC1
NC2
SGND PGND fSET
REVIEW TEMPERATURE
DERATING CURVE
C6 100pF
+
C3
100μF
VOUT
5V
8A
6.3V
REFER TO
SANYO POSCAP TABLE 2
RfSET
100k
RSET
8.25k
IMPROVE
EFFICIENCY
FOR r12V INPUT
SOT-323
CMSSH-3C
MARGIN CONTROL
4601A F16
Figure 16. 5V at 8A Design Without Differential Ampliï¬er
4601afb
21
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