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LTM4603HVEV-PBF View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
'LTM4603HVEV-PBF' PDF : 24 Pages View PDF
LTM4603HV
APPLICATIO S I FOR ATIO
Safety Considerations
The LTM4603HV modules do not provide isolation from
VIN to VOUT. There is no internal fuse. If required, a slow
blow fuse with a rating twice the maximum input current
needs to be provided to protect each unit from catastrophic
failure.
Layout Checklist/Example
The high integration of LTM4603HV makes the PCB board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current path, in-
cluding VIN, PGND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
tors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on pads.
• If vias are placed onto the pads, the the vias must be
capped.
• Interstitial via placement can also be used if necessary.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
Figure 17 gives a good example of the recommended
layout.
Frequency Adjustment
The LTM4603HV is designed to typically operate at 1MHz
across most input conditions. The fSET pin is typically left
open or decoupled with an optional 1000pF capacitor. The
switching frequency has been optimized for maintaining
constant output ripple noise over most operating ranges.
The 1MHz switching frequency and the 400ns minimum
off time can limit operation at higher duty cycles like 5V to
3.3V, and produce excessive inductor ripple currents for
lower duty cycle applications like 28V to 5V. The 5V and
3.3V drop out curves are modified by adding an external
resistor on the fSET pin to allow for wider input voltage
operations.
VIN
CIN CIN
GND
SIGNAL
GND
COUT
COUT
VOUT
4603HV F17
Figure 17. Recommended Layout
4603hvf
18
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