LTM4606 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTM4606' PDF : 28 Pages View PDF
LTM4606
PIN FUNCTIONS
VIN (Bank 1): Power Input Pins. Apply input voltage be-
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between VIN pins
and PGND pins.
VOUT (Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins (see figure below).
PGND (Bank 2): Power Ground Pins for Both Input and
Output Returns.
VD (Pins B7, C7): Top FET Drain Pins. Add more capacitors
between VD and ground to handle the input RMS current
and reduce the input ripple further.
DRVCC (Pins C10, E11, E12): These pins normally connect
to INTVCC for powering the internal MOSFET drivers. They
can be biased up to 6V from an external supply with about
50mA capability, or an external circuit as shown in Figure
18. This improves efficiency at the higher input voltages
by reducing power dissipation in the modules.
INTVCC (Pin A7): This pin is for additional decoupling of
the 5V internal regulator.
PLLIN (Pin A8): External Clock Synchronization Input to the
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor. Apply a clock above 2V and below
INTVCC. See the Applications Information section.
FCB (Pin M12): Forced Continuous Input. Connect this pin
to SGND to force continuous synchronization operation at
TOP VIEW
MPGM
12
COMP
11
RUN
SGND
10
TRACK/SS
9
PLLIN
VD
8
INTVCC
7
6
5
4
3
2
1
ABCDE F GH J K LM
VIN
BANK 1
PGND
BANK 2
VOUT
BANK 3
low load, to INTVCC to enable discontinuous mode opera-
tion at low load or to a resistive divider from a secondary
output when using a secondary winding.
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-Start
Pin. When the module is configured as a master output,
then a soft-start capacitor is placed on this pin to ground
to control the master ramp rate. A soft-start capacitor can
be used for soft-start turn-on as a standalone regulator.
Slave operation is performed by putting a resistor divider
from the master output to ground, and connecting the
center point of the divider to this pin. See the Applications
Information section.
MPGM (Pins A12, B11): Programmable Margining Input.
A resistor from these pins to ground sets a current that
is equal to 1.18V/R. This current multiplied by 10kΩ will
equal a value in millivolts that is a percentage of the 0.6V
reference voltage. See the Applications Information section.
To parallel LTM4606s, each requires an individual MPGM
resistor. Do not tie MPGM pins together.
fSET (Pin B12): Frequency set internally to 800kHz. An
external resistor can be placed from this pin to ground
to increase frequency. This pin can be decoupled with a
1000pF capacitor. See the Applications Information section
for frequency adjustment.
VFB (Pin F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to VOUT with a 60.4k preci-
sion resistor. Different output voltages can be programmed
with an additional resistor between the VFB and SGND pins.
See the Applications Information section.
MARG0 (Pin C12): LSB Logic Input for the Margining
Function. Together with the MARG1 pin, the MARG0 pin
will determine if a margin high, margin low, or no margin
state is applied. The pin has an internal pulldown resistor
of 50k. See the Applications Information section.
MARG1 (Pins C11, D12): MSB Logic Input for the Margin-
ing Function. Together with the MARG0 pin, the MARG1 pins
will determine if a margin high, margin low, or no margin
state is applied. The pins have an internal pulldown resistor
of 50k. See the Applications Information section.
SGND (Pins D9, H12): Signal Ground Pins. These pins
connect to PGND at output capacitor point.
4606f
7
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