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Figure 7 is a typical 1.544 Mbps T1 application of the
LXT301Z. The LXT301Z is shown with a typical T1/ESF
framer. An LXP600A Clock Adapter (CLAD) provides the
2.048 MHz system backplane clock, locked to the recov-
ered 1.544 MHz clock signal. The power supply inputs are
tied to a common bus with appropriate decoupling capaci-
tors installed (68 µF on the transmit side, 1.0 µF and 0.1 µF
on the receive side).
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