LXT332 View Datasheet(PDF) - LevelOne
Part Name
Description
MFG CO.
'LXT332' PDF : 32 Pages View PDF
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Receive clock period
DSX-1
W3:
èåê çéå æìê
QV
E1
W3:
éêä éåå èêæ
QV
Receive clock duty cycle
5&/.G éí
èí
çí
QV
Receive clock pulse width DSX-1 W3:+
ëèä êëé êåä
QV
High
E1
W3:+
ìäè ëéé ëäê
QV
Receive clock pulse width DSX-1 W3:/
ëèä êëé êåä
QV
Low
E1
W3:/
ìäè ëéé ëäê
QV
RPOS / RNEG to RCLK ris- DSX-1
W685
èí ëæé
¤
QV
ing setup time
E1
W685
èí ìäé
¤
QV
RCLK rising to RPOS /
RNEG hold time
DSX-1
W+5
èí ëæé
¤
QV
E1
W+5
èí ìäé
¤
QV
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Elastic store not in over-
flow or underflow.
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Master clock frequency
DSX-1
0&/.
¤
ìïèéé
E1
0&/.
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ëïíéå
Master clock tolerance
0&/.W
¤
‘èí
Master clock duty cycle
0&/.G
éí
¤
Transmit clock frequency
DSX-1
7&/.
¤
ìïèéé
E1
7&/.
¤
ëïíéå
Transmit clock tolerance
7&/.W
¤
‘èí
Transmit clock duty cycle
7&/.G
ìí
¤
TPOS/TNEG to TCLK setup time
W687
èí
¤
TCLK to TPOS/TNEG Hold time
W+7
èí
¤
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