Product Specification
AU OPTRONICS CORPORATION
Note1: Start from left side
M215HW01 VC
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Note2: Input signals of odd and even clock shall be the same timing.
6.4 Timing Characteristics
Basically, interface timing described here is not actual input timing of LCD module but close to
output timing of SN75LVDS82DGG (Texas Instruments) or equivalent.
Item
Data CLK
Symbol
Tclk
Period
H-section Display Area
Blanking
Period
V-section Display Area
Blanking
Frame Rate
Th
Tdisp(h)
Tblk(h)
Tv
Tdisp(h)
Tblk(h)
F
Min
40
1034
960
74
1088
1080
8
50
Typ
75
1060
960
100
1120
1080
40
60
Max
90
2047
960
1087
2047
1080
967
75
Unit
[MHz]
[Tclk]
[Tclk]
[Tclk]
[Th]
[Th]
[Th]
[Hz]
Note : DE mode only
document version 0.1
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